P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Read Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
33 MHz
Min
40 MHz
Min
No.
Symbol
Max
Max
Unit
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold(c)
8
3
5
2
ns
ns
General Timing Responses
3
tCHSV
tCLSH
tCLAV
Status Active Delay
0
0
0
0
0
15
15
15
15
0
0
0
0
0
12
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
Status Inactive Delay
5
AD Address Valid Delay and BHE
Address Hold
6
tCLAX
tCHDX
tCHLH
tLHLL
8
Status Hold Time
9
ALE Active Delay
15
12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
99
ALE Width
tCLCL–10=20
tCLCL–5=20
tCHLL
tAVLL
ALE Inactive Delay
15
12
AD Address Valid to ALE Low(a)
AD Address Hold from ALE Inactive(a)
AD Address Valid to Clock High
AD Address Float Delay
MCS/PCS Active Delay
MCS/PCS Hold from Command Inactive(a)
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low(a)
Control Active Delay 1(b)
DEN Inactive Delay
tCLCH –2
tCLCH –2
tLLAX
tCHCL–2
tCHCL –2
tAVCH
tCLAZ
0
0
tCLAX=0
15
15
tCLAX=0
12
12
tCLCSV
tCXCSX
tCHCSX
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
0
0
tCLCH–2
tCLCH–2
0
0
15
0
0
12
0
15
15
15
0
12
12
12
0
0
Control Active Delay 2(b)
ALE High to Address Valid
PCS Active to ALE Inactive
0
0
10
12
7.5
10
tPLAL
20
18
Read Cycle Timing Responses
24
25
26
27
28
29
41
59
66
67
68
tAZRL
tCLRL
AD Address Float to RD Active
RD Active Delay
0
0
ns
ns
ns
ns
ns
ns
0
15
15
0
10
12
tRLRH
tCLRH
tRHLH
tRHAV
tDSHLH
tRHDX
tAVRL
RD Pulse Width
2tCLCL–15=45
2tCLCL–10=40
RD Inactive Delay
0
0
RD Inactive to ALE High(a)
RD Inactive to AD Address Active(a)
DS Inactive to ALE Active
RD High to Data Hold on AD Bus(c)
A Address Valid to RD Low(a)
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to A Address Valid
tCLCH–3
tCLCH–2
tCLCL–10=20
tCLCL–5=20
tCLCH–2=11.5
tCLCH–2=9.25
0
0
ns
ns
ns
ns
tCLCL+ tCHCL–3
tCLCL+ tCHCL–1.25
tCHCSV
tCHAV
0
0
15
15
0
0
10
10
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
c
Equal loading on referenced pins.
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186ED/EDLV Microcontrollers
65
AMD [ AMD ]
