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the drive capability of the Transmitter and the termination circuit for multidrop transmis-
sion lines. Similarly, several Transmit bytes can be multiplexed to one Receiver. There
are no drive considerations in this case.
Figure 7-12 shows an example of an unbalanced mode of operation in which one
Transmitter is connected to three Receivers.
Fig u re 7 -1 2 Un b a la n c e d Co n fig u ra t io n Ex a m p le : On e Tra n s m it t e r t o Th re e Re c e ive rs
TTL Data IN
8,
9,
10
+
Am7968
SEROUT
–
X1
X2
OSC
Clock
X1
X1
X1
SERIN
CNB
SERIN
CNB
SERIN
CNB
VCC
IGM
IGM
8,
9,
8,
9,
8,
9,
Am7969
Am7969
Am7969
10
10
10
TTL Data OUT
12330E-34
Note that in the Unbalanced Configuration, attention has to be given to where a Sync
will be needed. Either the Auto-Repeat Receiver Configuration should be used or a
Sync must be provided every (R + 1) bytes, where R is the number of Receivers
cascaded together. More information on proper use and requirement of SYNC, refer to
Appendix C, TAXI TIP #8903.
8 .0 TES T MODE
The Phase Locked Loops (PLLs) in the TAXlchips are designed to run within a fre-
quency range that has been set for maximum efficiency and accuracy. The lower limit of
this frequency range is 40 MHz.
In Test Mode, the PLLs of the Transmitter and the Receiver are disconnected and the
internal clock is applied from an external source. This allows the TAXls to function at a
much slower speed. This mode was designed to simplify the testing of TAXls in an
automatic testing production environment. A by-product of Test Mode is that it allows the
user to run the TAXls in systems that are slower than 4 MHz (the minimum byte rate). In
this mode there is no minimum frequency.
A system that needs to transfer data at LOW byte data rates can normally be imple-
mented without modifying the standard setup, and Test Mode need not be used. When
there is no data to be sent, the TAXlchips will keep the line active by sending Syncs.
86
TAXIchip Integrated Circuits Technical Manual
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