AMD
The serial link will operate in the 40 to 175 MHz range as determined by the byte rate
clock, but the byte data rate will be determined by how often the user strobes the TAXI
Transmitter. The transmission speed is transparent to the user.
Some applications may have a serial link bandwidth limitation. Typically, this means that
the media connecting the Transmitter to the Receiver can only handle serial data rates
that are lower than 40 MHz. The user can run the TAXlchips in Test Mode in order to
overcome the 40 MHz lower frequency limitation.
For convenience in the following discussions, encoded data width n has been set to 10,
corresponding to an 8-bit input byte, (i.e. DMS = LOW).
Since the multiplying PLL is turned off in Test Mode, an external clock source must be
supplied to the TAXls. In normal (non-test) mode, the Transmitter PLL multiplies the
byte clock by 10. The new 10X clock is called the bit clock or bitclk, and is used to
transmit the serial data. The Receiver PLL generates the same type of bitclk to decode
the incoming data and to track and follow any fluctuations in the transmission frequency
of the incoming data.
In test mode the Transmitter PLL is disconnected and the internal clock multiplier is
switched out. The internal logic is now clocked directly by the signal applied to the CLK
pin. The input to the CLK pin now becomes the bitclk and must be supplied by the user.
On the Receiver side, the internal data tracking PLL is disconnected in Test Mode. An
external clock recovery circuit must be used to allow the Receiver to track the incoming
serial data stream. This recovered bitclk is supplied to X1. Either a digital PLL or an
analog PLL (for faster rates) can be used for clock recovery as shown in Figure 8-2.
The Transmitter and Receiver Test Mode connections and functionality are given in the
following section.
8 .1 Tra n s m it t e r Co n n e c t io n s
Refer to Figure 8-1.
The TLS pin is left floating. This is the pin that puts the Transmitter in Test Mode.
The RESET pin is left floating. RESET pin function is described in Appendix C, TAXI TIP
#89-02. The X2 pin is grounded.
SERIN is left floating (D/C = Do Not Connect).
The DMS pin is set in the appropriate state for 8-, 9- or 10-bit mode as desired by the
user.
The CLK is now an input for bitclk (the bit rate clock). This means that if the serial
transmission rate is to be 1.5 Kbits/s, CLK must be 1.5 kHz.
The ACK pin is raised only when a Sync byte is detected in the Transmitter’s shifter
latch (note that if STRB is lowered before ACK is seen, ACK will be suppressed. See the
STRB/ACK description in Section 7.1).
The X1 input is the reset pin for the internal state machines and can be left unconnected
in operational systems. For testing purposes, the following steps are to be taken upon
power up or initialization.
1. X1 should be kept HIGH and the Transmitter bitclked about 15 times
2. X1 should be lowered and the Transmitter bitclked about 200 times.
87
TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
