AMD
8 .2 Re c e ive r Co n n e c t io n s
Refer to Figure 8-2.
Grounding SERIN– puts the Receiver in Test Mode. SERIN+ is a single ended 100K
ECL NRZ input.
The X1 pin now becomes the bit rate clock input (bitclk), just like the CLK pin on the
Transmitter.
The CLK pin remains a byte rate CLK out.
8 .3 Tim in g Re la t io n s h ip s in Te s t Mo d e
The timing parameters in Test Mode are similar to the parameters in standard mode.
Propagation delay values remain the same, however bit time relationships are now
calculated with respect to the new bit times. For example, using a bitclk = 1.0 kHz, which
is a 1 ms period, the byte time t35 = 10 bits x 1 ms = 10 ms. In the same way t37, which is
the CLK falling to STRB rising delay is now [2 (t35/n) + 15 ns] = 2.015 ms. Note that
Setup and Hold times for SERIN to X1 are not specified and must be determined for
each application.
Fig u re 8 -2
Re c e ive r Te s t Mo d e Co n n e c t io n s
Normal
Function
Single Ended
Input From
Transmitter
DSTRB
SERIN+
CNB
DATA STROBE
SERIN–
X1
DATA OUT
8, 9, 10
Am7969
X2
CMD STROBE
RESET
Clock Recovery
Circuit
Digital or Analog
PLL
CSTRB
VLTN
COMMAND OUT
4, 3, 2
CLK
DMS
Byte Rate CLK Out
IGM
DMS Can Be
Set For 8, 9, or
10-Bit Mode
Normal
Function
12330E-36
89
TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
