AMD
This serves to flush all extraneous data from the buffers and reset all internal state
machines. Once this is completed the Transmitter may be Strobed. X1 should be left in
the LOW state upon completion of the initialization.
The STRB input must now be strobed only once every n = 10 bitclk pulses or more. This
will allow time for an 8 bit wide byte to be encoded to 10 bits and shifted out one bit
every clock pulse.
The parallel data input pins are provided with new data every 10 bitclk pulses. Setup
and hold times remain the same as in non-Test Mode with respect to STRB. (In the
non-Test modes, the clock rate is the byte rate and a new data word and a strobe is
provided every clock pulse. In test mode, the clock rate is the bit rate so the new data
word and strobe are provided every n clock pulses).
In Test Mode the Receiver expects only single ended data. Thus only one of the
SEROUT lines from the Transmitter is used. However, both lines must have pulldown
resistors to electrically balance the outputs.
Fig u re 8 -1
Tra n s m it t e r Te s t Mo d e Co n n e c t io n s
Divide By n
or Byte Rate
Clock
N/C
TLS
ACK
X1
STROBE
Data IN
8, 9, 10
X2
RESET
Am7968
Bit Rate
Clock
CLK
Generator
Command IN
4, 3, 2
N/C = Test Mode
CLS
DMS
SEROUT+
SEROUT–
Can Be Set
for 8, 9, or
10-Bit Mode
300 Ω
300 Ω
To Receiver
12330E-35
Media Interface
88
TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
