AMD
Fig u re 7 -9
Re c e ive r Tim in g in Au t o -Re p e a t Co n fig u ra t io n
Serial
Data
Sync
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
CNB1
IGM1
CNB2
IGM2
CNB3
IGM3 =
CNB1
12330E-31
Note: IGM3 = CNB1 so RX1 is now ready to receive new data. The cycle can now be repeated.
7 .3 .2 Tim in g Lim it a t io n s o f t h e Au t o -Re p e a t Co n fig u ra t io n
Note, however, that the t46 delay adds up as it ripples through the daisy chain. If the total
delay from the first to the last Receiver in the cascade is greater than 1 byte time,
parallel data will output 1 byte time later on some Receivers than on others.
The following example is for t46 = 20 ns and a 12.5 MHz byte rate, the time between the
start of one byte to the start of the next is 80 nanoseconds. When IGM on the last
Receiver goes HIGH forcing the CNB1 on the first one to go LOW, it will take 20 x R ns
(where R is the number of Receivers in cascade) before the last IGM goes LOW again,
(allowing CNB on the first Receiver to go HIGH).
In order for the first Receiver to capture the next byte its CNB cannot remain LOW for
more than X ns (where X must be less than 1 byte period).
X = (20 x R1) + (inverter delay) + (CNB to CLK set-up)
(R1 is the number of receivers that can be connected in cascade in this format)
The CNB to CLK set-up time is specified as t47 = [(byte time/n) –32 ns]
In 8 Bit mode at 12.5 Mbyte/s, CNB to clock setup = - [(80/10) –32] = 24 ns
Figure 7-10 demonstrates an alternative scheme which will allow a virtually unlimited
number of receivers to be cascaded. The fan-out of the inverter dictates the number of
AND gates that can be driven. Multiple inverters can be connected to the last IGM
output if needed. Using this scheme guarantees that all of the receivers in cascade will
84
TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
