Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 54. Supported PCI Bus Commands
C/BE[3:0]#
Command Type
Supported As Target Supported As Initiator
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
No
No
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Reserved
No
Memory Read
Memory Write
Reserved
Yes
Yes
No
No
Yes
Yes
Yes1
No
Yes1
Yes2
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Reserved
Memory Read Line
Memory Write & Invalidate
No3
No
No
No
1. Memory Read Multiple and Read Line are treated as Memory Reads.
2. Memory Write & Invalidate commands are treated as Memory Writes.
3. Must be enabled by bit 15 MCSR.
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