Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
EXPANSION BIOS ROMS
Data Sheet
able code is determined by the contents of the first
three locations (starting at offset 0h) and a byte check-
sum over the defined length. The defined length is
specified in the byte at address offset 0002h. Table 52
lists each field location by its address offset, its length,
its value, and description.
This section provides an example of a typical PC-com-
patible expansion BIOS ROM. Address offsets 0040h
through 007Fh represent the portion of the external nv
memory used to boot-load the S5335 controller.
Whether the expansion ROM is intended to be execut-
Table 52. PC Compatible Expansion ROM
Byte Offset Byte Length
Binary Value
Description
Example
55h
0h
1
55h
AAh
var.
var.
var.
var.
var
BIOS ROM signature byte 1
BIOS ROM signature byte 2
Length in multiples of 512 bytes
Entry point for INIT function.
Reserved (application unique data)
Pointer to PCI Data Structure (see Table 53)
user-defined
1h
1
AAh
01h
2h
1
3h
4
7h-17h
18h-19h
20h-3Fh
17h
2
32h
The following represents the boot-load image for the S5335 controller’s PCI configuration register:
40h
42h
44h
45h
46h
48h
49h
4Ch
4Dh
4Eh
4Fh
50h
2
2
1
1
2
1
3
1
1
1
1
1
[your vendor ID]
[your device ID]
not used
10e8h
4750h
00h
[Bus Master Config.]
not used
80h
[your revision ID]
[your class code]
not used
FF0000h
[your latency timer #]
[your header type]
[self-test if desired]
C0h, C1h or C2h
00h
00h
80h or 00h
C0h, C1h or
C2h
FFh
51h
52h
53h
54h
58h
5Ch
60h
64h
1
1
1
4
4
4
4
4
FFh
E8h
E8h
10h
10h
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
[base addr. #1]
[base addr. #2]
[base addr. #3]
[base addr. #4]
[base addr. #5]
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DS1657 90
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
