Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Read accesses from the S5335 operation registers
(S5335 as a target) are shown in Figure 47. The
S5335 conditionally asserts STOP# in clock period 3 if
the initiator keeps FRAME# asserted during clock
period 2 with IRDY# asserted (indicating a burst is
being attempted). Wait states may be added by the ini-
tiator by not asserting the signal IRDY# during clock 3
and beyond. If FRAME# remains asserted, but IRDY#
is not asserted, the initiator is just adding wait states,
not necessarily attempting a burst.
target disconnect and occurs when a read attempt is
made to an empty S5335 FIFO. The assertion of
STOP# without the assertion of TRDY# indicates that
the initiator should retry the operation later.
When burst read transfers are attempted to the S5335
operation registers, STOP# is asserted during the first
data transfer to indicate to the initiator that no further
transfers (data phases) are possible. This is a target-
initiated termination where the target disconnects after
the first data transfer. Figure 48 shows the signal rela-
tionships during a burst read attempt to the S5335
operation registers.
There is only one condition where accesses to S5335
operation registers do not return TRDY# but do assert
STOP#. This is called a target-initiated termination or
Figure 47. Single Data Phase PCI Bus Read of S5335 Registers (S5335 as Target)
2
3
1
4
5
FRAME
AD[31:0]
#
(I)
(T)
(I)
ADDRESS
DATA
(I)
BUS COMMAND
BYTE ENABLES
C/BE[3:0]#
IRDY#
(I)
(T)
TRDY#
DEVSEL#
STOP#
(T)
(T)
(I)
(T)
=
=
DRIVEN BY INITIATOR
DRIVEN BY TARGET
Figure 48. Burst PCI Bus Read Attempt to S5335 Registers (S5335 as Target)
2
3
1
4
5
PCI CLOCK
FRAME #
AD[31:0]
(I)
(T)
(I)
DATA
ADDRESS
C/BE[3:0]#
IRDY#
BUSCOMMAND
BE(2)
BYTE ENABLES (1)
(I)
(I)
(T
)
TRDY#
(T
)
DEVSEL#
STOP#
(T
)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
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