Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 44. Type 0 Configuration Read Cycles
1
3
NOTE
2
4
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
IF FRAME # STILL ASSERTED
DURING CLOCK 2, CONTROLLER
ASSERTS STOP# DURING 3
(I)
(I)
(T)
DRIVEN BY CONTROLLER
DURING CLOCK 3
DATA
ADDRESS
CONFIG. READ CMD
BYTE ENABLES
(I)
(I)
(T)
DRIVEN BY CONTROLLER
DURING CLOCKS 2,3 +4
TRDY#
(I)
IDSEL
DRIVEN BY CONTROLLER
DURING CLOCKS 2,3 +4
(T)
DEVSEL#
SELECT
CONDITION
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 45. Type 0 Configuration Write Cycles
1
2
3
4
NOTE
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
FRAME # DEASSERTED
IN CLOCK 2, SIGNIFIES
ONLY ONE DATA PHASE
(I)
(I)
DATA
ADDRESS
CONFIG WRITE CMD
BYTE ENABLES
(I)
(I)
DRIVEN BY CONTROLLER
DURING CLOCKS 2+3
(T)
TRDY#
(I)
IDSEL
DRIVEN BY CONTROLLER
DURING CLOCKS 2+3
(T)
DEVSEL#
SELECT
CONDITION
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
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