Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
PCI BURST TRANSFERS
Data Sheet
PCI Read Transfers
The S5335 responds to PCI bus memory or I/O read
transfers when it is selected (target). As a PCI bus ini-
tiator, the S5335 controller may also produce PCI bus
memory read operations.
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address incre-
menting and 80486 cache line fill sequencing. The
exact ordering scheme for a bus transaction is defined
by the state of the two least significant AD lines during
the address phase. The decoding for these lines is
shown below:
Figure 46 depicts the fastest burst read transfer possi-
ble for the PCI bus. The timings shown in Figure 46
are representative of the S5335 as a PCI initiator with
a fast, zero-wait-state memory target. The signals
driven by the S5335 during the transfer are FRAME#,
C/BE[3:0]#, and IRDY#. The signals driven by the tar-
get are DEVSEL# and TRDY#. AD[31:0] are driven by
both the target and initiator during read transactions
(only one during any given clock). Clock period 2 is a
required bus turn-around clock which ensures bus
contention between the initiator and target does not
occur.
AD[1:0]
0 0
Burst Order
Linear sequence
Reserved
0 1
Targets drive DEVSEL# and TRDY# after the end of
the address phase (boundary of clock periods 1 and 2
of Figure 46). TRDY# is not driven until the target can
provide valid data for the PCI read. When the S5335
becomes the PCI initiator, it attempts to perform sus-
tained zero-wait state burst reads until one of the
following occurs:
1 0
Cacheline Wrap Mode
Reserved
1 1
The S5335 supports both the linear and the cache line
burst ordering. When the S5335 controller is an initia-
tor, it always employs a linear ordering.
•
•
•
•
The memory target aborts the transfer
PCI bus grant (GNT#) is removed
The PCI to Add-On FIFO becomes full
Some accesses to the S5335 controller (as a target)
can not be burst transfers. For example, the S5335
does not allow burst transfers when accesses are
made to the configuration or operation registers
(including the FIFO as a target). Attempts to perform
burst transfers to these regions cause STOP# to be
asserted during the first data phase. The S5335 com-
pletes the initial data phase successfully, but asserting
STOP# indicates that the next access needs to be a
completely new cycle. Accesses to memory or I/O
regions defined by the Base Address Registers 1-4
may be bursts, if desired.
A higher priority (Add-On to PCI) S5335 trans-
fer is pending (if programmed for priority)
•
•
The read transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5335 as Initiator)
3
1
2
4
5
6
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
(I)
(I)
(T)
(T)
DATA (1)
(T)
ADDRESS
DATA (2)
DATA (3)
BUS COMMAND
BYTE EN (2)
BYTE ENABLES (1)
BYTE EN (3)
(I)
(I)
(T)
TRDY#
(T)
DEVSEL#
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
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DS1657 94
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
