S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Table 3. Output Select Matrix
Configuration
Number
Select Pins
Output Fed
to FBCLK
Output Phase Relationships
FOUT0 FOUT1 FOUT2 FOUT3 HFOUT
÷4
÷8
PHSEL1 PHSEL0
X2FOUT
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
FOUT0–FOUT3
HFOUT
0
2(0)
0/2
0
0
2(0)
0/2
Q
0
2(0)
0/2
2Q
Q
0
2(0)
0/2
3Q
2Q
Q
0/2
0
0
2(0)
4(0)
0
2
2(0)
3
X2FOUT (÷8)
FOUT0
0/4
4
0/2
0
2(0)
2(–Q)
5
FOUT1
–Q
–2Q
–3Q
2(0)
0/2
0
0
–Q/2
–2Q/2
–3Q/2
0
–Q
6
FOUT2
–Q
–2Q
2(Q)
Q/2
–t
0
–2Q 2(–2Q)
–3Q 2(–3Q)
7
FOUT3
–Q
2(2Q)
2Q/2
t
0
8
HFOUT
2(3Q)
3Q/2
Q
2(0)
4(0)
0
9
X2FOUT (÷8)
FOUT0
0/4
10
11
12
13
14
15
16
17
18
19
20
21
0/2
0
t
2(0)
2(t)
FOUT1
t
0
2t
Q+t
Q–t
0
t/2
FOUT2
–t
–2t
–Q–t
2(–t)
–t/2
t
0
–t/2
–Q/2
0
–t
2(–t)
2(–Q)
4(0)
0
FOUT3
–Q
2(0)
0/2
0
–Q+t
2(t)
t/2
–Q
2(0)
HFOUT
2(Q)
Q/2
3t
X2FOUT (÷8)
FOUT0
0/4
2t
0/2
0
2(0)
2(–t)
2(–2t)
2(–3t)
4(0)
0
FOUT1
–t
0
t
2t
–t/2
–2t/2
–3t/2
0
–t
FOUT2
–2t
–3t
2(0)
0/2
–t
0
t
–2t
–3t
2(0)
FOUT3
–2t
2(t)
t/2
–t
0
HFOUT
2(2t)
2t/2
2(3t)
3t/2
X2FOUT (÷8)
0/4
Notes: 1. “0” implies the output is aligned with REFCLK.
2. “t” implies the output lags REFCLK by a minimum phase delay.
3. “Q” implies the output lags REFCLK by 90° of phase
4. “–t” implies the output leads REFCLK by a minimum phase delay.
5. “–Q” implies the output leads REFCLK by 90° of phase.
6. “2( )” implies the output is at twice the frequency of REFCLK.
Legend
Table
entry
Table
entry
Table
entry
Waveform
Waveform
Waveform
REFCLK
2(0)
REFCLK
REFCLK
Q
2Q
–Q
0
t
0/2
4(0)
0/4
2t
–t
–t 0 t 2t
–90° 0° 90° 180°
Applied Micro Circuits Corporation
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Page 5
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