S4402/S4403
BiCMOS PLL CLOCK GENERATOR
HFOUT, or X2FOUT) is externally connected to
the feedback input (FBCLK) to produce the result-
ing waveforms shown in the appropriate row in the
table. The last seven columns specify the resulting
phase and frequency relationships of each output
to the user clock input (REFCLK). A negative value
indicates the time by which the output rising edge
precedes the input (REFCLK) rising edge. A posi-
tive value is the time by which the rising edge of
the output follows the rising edge of the input
clock.
FUNCTIONAL DESCRIPTION
Frequency and Phase Controls
The S4402/S4403 clock generators provide multiple
outputs that are synchronized in both frequency and
phase to a periodic clock input. Two select pins and
an external feedback path allow the user to phase-
adjust the six outputs (FOUT0–FOUT3, HFOUT, and
X2FOUT) relative to the input clock REFCLK, as well
as control their frequency.
Table 1. Example Phase Resolution
The DIVSEL input controls the programmable divider
that follows the voltage controlled oscillator (VCO).
This doubles the lock range of the PLL by allowing
the user to select a VCO frequency divided by four
(DIVSEL Low) or by eight (DIVSEL High).
FOUT0–3
Freq
Divider
Select
VCO
Freq
Min Phase
Resolution
80 MHz
66 MHz
50 MHz
40 MHz
40 MHz
33 MHz
25 MHz
20 MHz
4
4
4
4
8
8
8
8
320 MHz
266 MHz
200 MHz
160 MHz
320 MHz
266 MHz
200 MHz
160 MHz
3.125 ns
3.75 ns
5.0 ns
The frequency of the four FOUT0–FOUT3 outputs
(and the duplicate set of the four FOUT0A–
FOUT3A outputs on the S4403) is determined by
the REFCLK clock frequency and the output that is
tied back to the FBCLK input. In addition, the
X2FOUT TTL output provides a clock signal identi-
cal to the FOUT0 output in the divide-by-four
mode, and twice the FOUT0 frequency (maximum
frequency of 80 MHz) in the divide-by-eight mode.
The HFOUT TTL output provides a clock signal
that is in phase with the FOUT0 output, but at half
the FOUT0 frequency in both the divide-by-four
and divide-by-eight modes. Refer to the Output
Select Matrix in Table 3 for the specific relation-
ships.
6.25 ns
3.125 ns
3.75 ns
5.0 ns
6.25 ns
Table 2. Phase Selections
PHSEL1 PHSEL0
Phase Relationship
0
0
All at same phase
0
1
FOUT0–FOUT3 outputs skewed by
90 degrees from each other
1
1
0
1
FOUT1 leads FOUT0 by minimum
phase, FOUT2 lags FOUT0 by
minimum phase, and FOUT3 lags
FOUT0 by 90 degrees
Phase adjustments can be made in increments as
small as 3.125 ns. The minimum phase delay be-
tween FOUT0–FOUT3 signals is a function of the
VCO frequency. The VCO frequency can be deter-
mined by multiplying the output frequency by the di-
vide-by ratio of four or eight, controlled by DIVSEL.
The minimum phase delay t is equal to the period of
the VCO frequency:
FOUT1 lags FOUT0 by minimum
phase, FOUT2 lags FOUT1 by
minimum phase, and FOUT3 lags
FOUT2 by minimum phase
Example:
In a typical system, designers may need several
low-skew outputs, one early clock, one late clock,
a clock at half the input clock frequency, and one
at twice the input clock frequency. This system re-
quirement can be met by setting PHSEL1 to 1,
PHSEL0 to 0, and feeding back FOUT0 to the
FBCLK input (Row 10 of Table 3). The result is
that FOUT0 will be phase-aligned to REFCLK,
FOUT1 will lead REFCLK by a minimum phase
delay, FOUT2 will lag REFCLK by a minimum
phase delay, FOUT3 will phase-lag REFCLK by
90°, HFOUT will be phase-aligned with REFCLK
but at half the frequency, and X2FOUT will be ei-
ther phase-aligned at the same frequency as the
reference clock if DIVSEL = 0, or at twice the fre-
quency if DIVSEL = 1.
t = 1 / VCO freq
Since the VCO can operate in the 160 MHz to
320 MHz range, minimum phase delay values can
range from 6.25 ns to 3.125 ns. Table 1 shows vari-
ous FOUT/VCO frequencies and the associated
phase resolution.
The PHSEL1 and PHSEL0 inputs allow the user to
select several phase relationships among the four
FOUT0–FOUT3 TTL clock outputs. These choices
can be seen in Table 2, and the Output Select
Matrix provided in Table 3 describes the 21 output
configurations available to the user. The two “Se-
lect Pins” columns specify the signal levels on the
pins PHSEL0 and PHSEL1. These are active High
signals. The column entitled “Output Fed to
FBCLK” indicates which output (FOUT0–FOUT3,
Several other waveform examples and typical appli-
cations are provided on pages 7-8 and 7-9.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 2
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