S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Table 4. AC Specifications
S4402/3-66
S4402/3-80
Symbol
Description
Min
Max
Min
Max
Units
fVCO
fREF
VCO Frequency
REFCLK Frequency
160
10
7.0
-1.0
0
266
66
160
10
6.0
-1.0
0
320
80
MHz
MHz
ns
MPWREF
tPE
REFCLK Minimum Pulse Width
Phase Error between REFCLK and FBCLK
Phase Error Difference from Part to Part1
Output Skew2
0
750
400
55
0
750
400
55
ns
tPED
tSKEW
tDC
ps
0
0
ps
Output Duty Cycle3
45
20
10
40
3.75
-250
2
45
20
10
40
3.125
-250
2
%
fFOUT
fHFOUT
f2XFOUT
tPS
FOUT Frequency4
66
80
MHz
MHz
MHz
ns
HFOUT Frequency4
33
40
2XFOUT Frequency4
66
80
Nominal Phase Shift Increment
Phase Shift Variation5
6.25
+250
7
6.25
+250
7
tPSJ
ps
tOFD
tOFE
tIRF
Tpd OUTEN0–2 to FOUTs, Disable
Tpd OUTEN0–2 to FOUTs, Enable
Input Rise/Fall Time
ns
2
7
2
7
ns
1
3
1
3
ns
tORF
tLOCK
tj
FOUT Rise/Fall Time6
0.5
1.5
5
0.5
1.5
5
ns
Loop Acquisition Time7
ms
ps
Clock Stability8
500
500
1. Difference in phase error between two parts at the same voltage, temperature and frequency.
2. Output skew guaranteed for equal loading at each output.
3. Outputs loaded with 35pF, measured at 1.5V.
4. CLOAD = 35 pF.
5. All phase shift increments and variation are measured relative to FOUT0 at 1.5V.
6. With 35 pF output loading (0.8 V to 2.0 V transition).
7. Depends on loop filter chosen. (Number given is for example filter.)
8. Clock period jitter with all FOUT outputs operating at 66 MHz and loaded with 25pF using loop filter
shown. Parameter guaranteed, but not tested.
Figure 5. Timing Waveforms
MPW
PE
MPW
REF
REF
REFCLK
FBCLK
t
t
PE
t
t
SKEW
SKEW
FOUT0–3
HFOUT, X2FOUT
FOUT0–3
Output
Valid
Disabled
HFOUT, X2FOUT
t
t
OFD
OFE
OUTEN0–2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 9
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