BiCMOS PLL CLOCK GENERATOR
S4402/S4403
Enabling Outputs
Power Supply Considerations
The S4402 has two output-enable inputs that con-
trol which outputs toggle. (The S4403 has three
output-enable inputs.) When held LOW, OUTEN0
controls the frequency doubler output X2FOUT
and the half-frequency output HFOUT. OUTEN1
controls the FOUT0–FOUT3 outputs. The third in-
put on the S4403, OUTEN2, controls the duplicate
set of four outputs FOUT0A–FOUT3A. When an
output enable pin is held High, its associated out-
puts are disabled and held in a High state.
Power for the analog portion of the S4402/S4403
chips must be isolated from the digital power supplies
to minimize noise on the analog power supply pins.
This isolation between the analog and digital power
supplies can be accomplished with a simple external
power supply filter (Figure 3). The analog power
planes are connected to the digital power planes
through single ferrite beads (FB1 and FB2) or induc-
tors capable of handling 25 mA. The recommended
value for the inductors is in the range from 5 to
100µH, and depends upon the frequency spectrum of
the digital power supply noise. The ferrite beads
should exhibit 75Ω impedance at 10 MHz.
Filter
The FILTER output is a tap between the analog out-
put of the phase detector and the VCO input. This pin
allows a simple external filter (Figure 2) to be in-
cluded in the PLL. AMCC recommends the use of the
filter component values shown. This filter was chosen
for its ability to reduce the output jitter and filter out
noise on the REFCLK input. The filter components
should be in surface mounted packages with mini-
mum lead inductance.
Decoupling capacitors are also very important to mini-
mize noise. The decoupling capacitors must have low
lead inductance to be effective, so ceramic chip ca-
pacitors are recommended. Decoupling capacitors
should be located as close to the power pins as physi-
cally possible. And the decoupling should be placed
on the top surface of the board between the part and
its connections to the power and ground planes.
Figure 3. External Power Supply Filter
Figure 2. External PLL Filter
20
FB1
A +5V
A VCC
DIGITAL +5V
ANALOG +5V
0.1µF
10 µF
Tantalum
(optional)
0.1 µF
S4402
1.5k Ω
19
FB2
FILTER
DIGITAL GND
ANALOG GND
Test Capabilities
Reset
When the RESET pin is pulled low, all the internal
states go to zero one clock cycle (from the VCO or
REFCLK in the test mode) before the outputs go low.
After the chip is reset, the PLL requires a
resynchronization time of ≤5ms before lock is again
achieved.
The TSTEN input puts the S4402/S4403 into a test
mode and allows users to bypass the VCO and pro-
vide their own clock through the REFCLK input.
When TSTEN is High, the VCO is turned off and the
REFCLK signal drives the divider/phase adjust cir-
cuitry, directly sequencing the outputs. The TSTEN
and REFCLK inputs join the divider circuitry after the
initial divide-by-two stage. Therefore, REFCLK is di-
vided by two in the divide-by-four mode and divided
by four in the divide-by-eight mode.
Lock Detect
A lock detect function is provided by the LOCK out-
put. When REFCLK and FBCLK are within 2–4 ns of
each other, the PLL is in lock, and the LOCK output
goes High.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
