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S4402A-80/TD 参数 Datasheet PDF下载

S4402A-80/TD图片预览
型号: S4402A-80/TD
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Generator, 80MHz, BICMOS, PQCC28, PLASTIC, LCC-28]
分类和应用: 时钟信息通信管理外围集成电路晶体
文件页数/大小: 13 页 / 151 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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BiCMOS PLL CLOCK GENERATOR  
TYPICAL APPLICATIONS  
S4402/S4403  
The S4402/S4403 chips are designed to meet a  
large variety of system clocking requirements. Sev-  
eral typical applications are provided below.  
Clock Outputs  
at twice, equal to,  
or half the  
XTAL  
REFCLK  
S4402  
Application 1. High-Frequency, Low-Skew Clock  
Generation  
input frequency  
One of the most basic capabilities of the S4402/  
S4403 devices is generating multiple phase-  
aligned low-skew clocks at various multiples of the  
input clock frequency. For example, in a multiple-  
board system a half-frequency clock can be gener-  
ated for use across the backplane, where it is  
simpler to route a low-speed signal. This signal  
can then be doubled on the boards, and synchro-  
nization will be maintained.  
Application 2. Low-Skew Clock Distribution  
XTAL  
REFCLK  
S4402  
REFCLK  
One common problem in clocking high-speed sys-  
tems is that of distributing several copies of a sys-  
tem clock while maintaining low skew throughout  
the system. The S4402/S4403 devices guarantee  
low skew among all the clocks in the system, as  
they have effectively zero delay between their in-  
put and output signals, with an output skew of less  
than 400 ps. The user can also adjust the phases  
of the outputs in increments as small as 3.125 ns,  
for load and trace length matching.  
S4402  
REFCLK  
S4402  
REFCLK  
S4402  
Application 3. Delay Compensation  
REFCLK  
S4402  
Since the relative edges of the S4402/S4403 out-  
puts can be precisely controlled, these chips can  
be used to compensate for different delays due to  
trace lengths or to internal chip delays, simplifying  
board layout and bus timing. In the example  
shown, the two ASICs have a difference of several  
nanoseconds in their propagation delays. The  
S4402s ensure that the output signals are aligned,  
so that the data valid uncertainty on the com-  
mon bus is minimized.  
ASIC  
Input  
Clock  
REFCLK  
S4402  
ASIC  
Clock tree output  
Applied Micro Circuits Corporation  
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333  
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