Part Number S3098
Revision NC - Oct 17, 2001
S3098
FEATURES
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Low power operation
Silicon Germanium BiCMOS technology
Complies with Telcordia and ITU-T
specifications
Supports G.709 and 10 Gigabit Ethernet rates
Supports OC-192 to OC-192 with Forward
Error Correction (FEC) rates
Integrated phase lock loop
Postamp on serial input
VCO Tunable from 9.953 GHz to 10.709 GHz
155.52 MHz REFCLK input (or equivalent
FEC rate)
16-bit parallel, 622.08 Mbps LVDS data path
(or equivalent FEC rate)
Lock detect indicator
Low jitter CML differential or single-ended serial
interface
Recovered 622.08 MHz clock output
(or equivalent FEC rate)
Accepts Active High or Active Low signal detect
inputs for loss of light (programmable)
Accepts LVCMOS or LVPECL signal detect
inputs
Synthesizes parallel output clock during
loss-of-signal conditions
Power 1.3 W (typ)
Compact 15 mm x 15 mm 148-pin CBGA package
DEVICE SPECIFICATION
SONET/SDH/ATM OC-192 1:16 Low Power Receiver
w
/CDR/Postamp
APPLICATIONS
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SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
GENERAL DESCRIPTION
The S3098 low power 1:16 receiver with Clock/Data
Recovery (CDR) and integrated postamp is a fully inte-
grated O C-192 des er ialization/clock and data
recovery device. The S3098 receives an OC-192
scrambled NRZ serial signal and recovers the clock.
This recovered clock is then used to re-time and
demultiplex the data into 16 parallel lines. If a loss-of-
signal condition occurs (or LCKREFN is asserted
Low), the internal Phase Lock Loop (PLL) will lock to
the local 155.52 MHz Reference Clock (REFCLK) (or
equivalent FEC rate) to provide a stable clock for
down-stream purposes. The S3098 has a limiting
postamp on the serial input for small signal gain.
The low jitter LVDS interface guarantees compliance
with the bit error rate requirements of the Telcordia and
ITU-T standards. Figure 1,
System Block Diagram,
shows a typical network application.
Figure 1. System Block Diagram
16
AMCC
GANGES
GANGES II
or HUDSON
AMCC
S3097
TX
AMCC
S3098
RX
AMCC
S3090
TIA
AMCC
OTX
ORX
S3090
TIA
AMCC
S3098
RX
AMCC
S3097
TX
16
16
ORX
16
OTX
AMCC
GANGES
GANGES II
or HUDSON
AMCC Confidential and Proprietary
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
