SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
3. The SYNCRSTB will be removed (de-asserted
high) from the four controllers for a minimum 16
PCLK A,B,C,D clock cycles.
Clock Generation
The clock generation circuitry generates the 77.76
MHz PCLK A,B,C,D clock required for the byte wide
STS-12/STM-4 interface from the 311 MHz clock
(311TCLK) required for the byte wide STS-48/STM-
16 interface.
4. The transmit data clock (PCLK A,B,C,D) will con-
tinue to be stopped for a minimum 16 clock
cycles after reset is de-asserted and then start
clocking.
Bit Interleaved Parity - N
5. STS-12/STM-4 data out of the four controllers will
start to flow into the S3045. The S3045 will
search for a high pulse on the TIFP input pulses
on all four channels. If the four controllers are not
frame aligned in 250us this sequence will restart.
Bit Interleaved Parity-N (BIP-N) is a method of error
monitoring. Even parity is used for the BIP-8 calcula-
tion. The transmitting equipment generates an N-bit
code over a specified portion of the signal in such a
manner that the first bit of the code provides even
parity over the first bit of all N-bit sequences on the
covered portion of the signal, the second bit provides
even parity over the second bit of all N-bit se-
quences within the specified portion, etc. Even parity
is generated by setting the BIP-N bits so that there
are an even number of ones in each of all N-bit
sequences including the BIP-N.
Frame Control Counter
The frame counter receives the TIFP signals indicat-
ing the frame boundaries and counts 38,880 bytes (9
rows x 90 columns x 48 STS-1) to ensure that the
transmitter is receiving synchronous TIFP pulses.
The frame counter keeps track of the overhead bytes
so that proper location and insertion of bytes is ac-
complished.
B1 Parity Calculation
The frame control block outputs a frame synchro-
nous reset signal (SYNCRSTB) that frame aligns the
STS-12/STM-4 network interface processors. The
Transmit Input Frame Pulse (TIFP) signal indicates
to the frame counter the frame position of the input
data channel. If the transmitter does not get four
simultaneous TIFP signals after 250us the
SYNCRSTB pin is asserted low. The frame counter
controls the output mux on the scrambler to allow
scrambling, parity byte (B1) generation and inser-
tion, M1 calculations and insertions, Z0 calculations
insertions, and parity byte (B2) generations and in-
sertions.
This byte is allocated for regeneration section error
monitoring. This byte will be calculated using even
parity. Even parity is generated by setting the bit
interleaved parity bits so that there is an even num-
ber of ones in each monitored partition of the signal.
The interleaved even parity byte B1 is calculated
over the entire scrambled STS-48/STM-16 frame
and inserted into the B1 location of the next frame
before going through the scrambling process. The
computed bit interleaved parity is only placed in the
B1 byte of the first STS-1 signal of the STS-48/STM-
16 frame before scrambling (one B1 byte is valid in a
Figure 3. S3045 Synchronous Reset Functional Timing Diagram
PCLK A,B,C,D
16 cycles
16 cycles
TIFP A
TIFP B
TIFP C
TIFP D
TIFP D misaligned
SYNCRSTB
5
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
