S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
the byte following the last byte of the first row (last
C1 byte) of the STS-12/STM-4 section overhead.
This bit and all subsequent bits to be scrambled will
be added modulo 2 to the output from the X7 position
of the scrambler (A1, A2, or C1 bytes are not
scrambled). The scrambler will run continuously
throughout the complete STS-48/STM-16 frame. A
set of signals from the frame control counter block
controls when the scrambler is on, off, or reset.
ARCHITECTURE/FUNCTIONAL DESIGN
Transmit Operation
The S3045 transmit section performs the byte inter-
leaving stage in the processing of a transmit
SONET/SDH STS-48/STM-16 byte wide data
stream. It converts four byte wide STS-12/STM-4
data streams into a single byte serial STS-48/STM-
16 data stream. The byte interleaved parity (B1) is
calculated over the entire STS-48/STM-16 frame and
inserted into the appropriate B1 location. In each
STS-48/STM-16 frame there is one B1 byte located
in the first STS-1 frame. The M1 byte is calculated
(addition of four STS-12/STM-4 M1 bytes) and in-
serted into the number one STS-12/STM-4 M1
position. Zero is inserted into the number two, three,
and four STS-12/STM-4 M1 positions. The section-
trace bytes (J0/Z0) can be optionally inserted by
setting the J0/Z0SEL high. The SONET/SDH scram-
bler can be enabled or disabled by the SCRBENB
input.
Frame Synchronization
The four STS-12/STM-4 input data streams from the
four controllers must be frame aligned before this
data is fed into the S3045 since the S3045 does not
have any data buffering. The four controllers each
output an active high framing position signal that is
input into the TIFP inputs of the S3045 that marks
the frame alignment on the output bus. This signal
goes high for a single 77.76 MHz clock period during
the first synchronous payload envelope byte immedi-
ately following the C1 bytes. The TIFP A,B,C,D
inputs associated with each of the four STS-12/STM-
4 data streams must be high at the same time so as
to indicate frame alignment of all four data streams.
These frame pulses will indicate frame alignment
with the first payload byte of the STS-12/STM-4
frames. When frame alignment occurs, valid data will
start to be output by the next valid frame. Valid B1
and B2 parity bytes will be output on the following
frame. Otherwise random data will be clocked out of
the 311DATOUT[7:0] output. In the event that all
four pulses are not high at the same time (frames
are not exactly aligned), a reset sequence will be
generated by the S3045 to re-synchronize the four
data streams.
STS-48/STM-16 Byte Interleave Multiplexing
The byte interleave mux shown in Figure 2 takes in
the four byte wide STS-12/STM-4 data streams four
bytes at a time and outputs byte wide STS-48/STM-
16 data stream. The byte interleave mux inputs are
registered on the STS-12/STM-4 interface. The mux
first takes four bytes from the A input, followed by
four from B, four from C, and four from D. The pat-
tern is repeated as data on the A, B, C, and D inputs
are registered and passed into a four word deep
pipeline register. Each of the four data words are
then latched into holding registers. A counter at the
STS-48/STM-16 byte rate (311 MHz) controls a mux
that loads data into a register at the STS-48/STM-16
byte rate and is then transmitted. STS-48/STM-16
byte interleaving must be done four bytes at a time,
where as STS-3/STM-1 and STS-12/STM-4 is ac-
complished one byte at a time.
In order to guarantee the synchronization of the four
controllers, a reset sequence will be applied by the
S3045. This reset will align the four STS-12/STM-4
inputs for multiplexing. Note that parity errors may
be erroneously generated during this reset se-
quence. Figure 3 depicts the following synchroniza-
tion sequence.
Scrambler
The scrambler can be utilized in order to guarantee
a suitable bit pattern, which prevents a long se-
quence of 1’s or 0’s. The frame synchronous
scrambler can be optionally used to scramble the
STS-48/STM-16 data stream. The SONET scram-
bling generator polynomial of 1 + x6 + x7 with a
sequence length of 127 is used. The scrambler will
be reset to “1111111” on the most significant bit of
1. The SYNCRSTB will be asserted low to reset the
four controllers upon a misalignment of the four
TIFP pulses and will be held low for a minimum
16 PCLK A,B,C,D clock cycles (77.76 MHz).
2. The transmitter data clock (PCLK A,B,C,D) will
stop for a minimum 16 clock cycles while the
SYNCRSTB is asserted low.
4
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
