SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
It is important to note that in squelch mode there
may be up to 3.2 nsec shortening or lengthening of
the POCLK A,B,C,D cycle, resulting in an apparent
phase shift in the POCLK at the de-assertion of the
SD condition. Another similar phase shift will occur
when the SD condition is reasserted. Figure 8 de-
picts this operation.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is
low, a loopback from the transmitter to the receiver at
the serial data rate can be set up for diagnostic pur-
poses. In loopback mode the STS-48/STM-16
transmitter outputs (311DATOUT[7:0], 311CLKOUT
and an internally generated Frame pulse on the third
A2 byte (that is not accessible to the outside of the
chip)) are internally connected to the STS-48/STM-16
receiver inputs (311DATIN[7:0], 311CLKIN, and
FRAME). In loopback mode the STS-48/STM-16 trans-
mitter outputs (311DATOUT[7:0] and 311CLKOUT) are
still active.
In the normal operating mode with SQUELCHB input
inactive (high), there will be no phase discontinuities
at the POCLK A,B,C,D output during signal loss or
re-acquisition (assuming operation with continuous
clock from the CRU device such as the AMCC
S3040 or S3047). Figure 9 depicts this operation.
Byte wide Parity Calculation
Odd parity or even parity can be calculated using the
PIN A,B,C,D and POUT A,B,C,D data busses by set-
ting the PARSEL line high for even parity or low for
odd parity. Even parity is generated by setting the
parity bit so that there are an even number of ones
throughout the 9 bits. Odd parity is generated by
setting the parity bit so that there is an odd number
of ones throughout the 9 bits.
“Squelched Clock” Operation
Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state (squelched clock) if the
optical signal is removed or reduced below a fixed
threshold. This condition is accompanied by the ex-
pected deassertion of the Signal Detect (SD) output.
Reset Operation
The S3045 has been designed for operation with
clock recovery devices that provide continuous serial
clock for seamless down stream clocking in the
event of optical signal loss. For operation with an
optical transceiver that provides the “squelched
clock” behavior as described above, the S3045 can
be operated in the “squelched clock mode” using the
SQUELCHB input.
The RESET (RSTB) input forces all the internal logic
of the S3045 to its deasserted state. All of the se-
quential logic inside the S3045 will remain static for
as long as reset is asserted. The RESET input is
implemented using a schmitt type receiver. The RE-
SET input is asynchronous to the input clock.
RESET should be asserted for at least 30 nano sec-
onds after power up for proper operation. During
reset PCLK A,B,C,D and POCLK A,B,C,D will stop,
and SYNCRSTB will remain high.
In squelch mode, the 311CLKIN is used for all re-
ceiver timing when the SDLVPECL or SDLVTTL
inputs are in the active state. (SDLVPECL and
SDLVTTL are in opposite logical states.) When the
SDLVPECL or SDLVTTL inputs are placed in the
inactive state (usually by the de-assertion of the Sig-
nal Detect [SDLVPECL and SDLVTTL are in the
same logical state] from the optical transceiver/clock
recovery unit) the transmitter serial clock (311TCLK)
will be used to maintain timing in the receiver sec-
tion. This will allow the POCLK A,B,C,D to continue
to run and the parallel outputs to flush out the last
received characters and assume the all zero state
imposed at the serial data input.
9
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
