S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
7. Frame synchronous scrambling.
8. B1 calculation and insertion.
S3045 OVERVIEW
The S3045 byte interleave chip implements SONET/
SDH byte interleave functions required to multiplex/
demultiplex four STS-12/STM-4 data streams into a
single STS-48/STM-16 data stream. Each of the four
STS-12/STM-4 transmit/receive data streams uses
an 8-bit parallel interface with parity to maintain com-
patibility with industry standard network interface
processors. The STS-48/STM-16 data stream uses
an 8-bit parallel LVDS data path to be compatible
with the S3041/S3042 Mux/Demux chipset. The
block diagram in Figure 2 shows the basic operation
of the chip. This chip can be used with the S3041
and S3042 to implement the front end of SONET
equipment. The chip includes byte interleave cir-
cuitry along with B1 calculation, M1 calculation, J0/
Z0 insertion, and B1 verification circuitry. STS-48/
STM-16 data stream is monitored in the receive path
for OOF and LOS, and alarm outputs are generated.
9. STS-48/STM-16 compatible 8-bit wide 311 MHz
LVDS output (311DATOUT).
Receiver Operations
1. STS-48/STM-16 compatible 8-bit wide 311 MHz
LVDS input (311DATIN).
2. OOF and LOS states are monitored and alarms
are generated.
3. B1 extraction and calculation of the STS-48/STM-16
frame.
4. B1 calculation of the number one STS-12/STM-4
frame.
5. Frame synchronous descrambling.
6. B1 compare and error indication (B1ERR) genera-
tion for the STS-48/STM-16 frame.
The S3045 is divided into a transmitter section and a
receiver section. The sequence of operation is as
follows:
7. Insert the number one STS-12/STM-4 B1 parity byte
into the number one STS-12/STM-4 frame and insert
errors if any found in the STS-48/STM-16 B1 parity
byte.
Transmitter Operations
1. 32-bit LVTTL parallel input from four 8-bit STS-
12/ STM-4 data streams (PIN A,B,C,D) with parity
(PARIN A,B,C,D).
8. 32-bit (4 x 8 bit) parallel output of four STS-12/
STM-4 data streams (POUT A,B,C,D) with parity
output (PAROUT A,B,C,D).
2. Four Byte interleave conversion Mux.
3. Section-trace insertion (J0/Z0).
Suggested Interface Devices
4. M1 calculation (addition of four STS-12/STM-4
M1 values) and insertion into the number one
STS-12/STM-4 location.
AMCC
AMCC
AMCC
AMCC
AMCC
S3040/S3047
S3041
Clock Recovery Device
OC-48 Mux
5. M1 insertion of zero into STS-12/STM-4 number
two, three, and four locations.
S3042
OC-48 Demux
CONGO S1201 POS/ATM SONET Mapper
NILE S1202 ATM SONET Mapper
6. Four B2 parity byte calculations and insertions for
STS-1 frames after M1 insertions.
S3045 Acronym List
SDH
SEF
–
–
Synchronous Digital Heirarchy
Severely Errored Frame
BER
CDR
LOS
OOF
ORX
OTX
–
–
–
–
–
–
Bit Error rate
Clock and Data Recovery
Loss Of Signal
SONET –
Synchronous Optical Network
Synchronous Transport Module
Synchronous Transport Signal
STM
STS
–
–
Out Of Frame
Optical Receiver\
Optical Transmitter
2
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
