SONET/SDH OC-12 TO OC-48 MUX/DEMUX
RECEIVER OPERATION
S3045
Receive Frame Counter
The S3045 byte interleave receive section converts
the byte wide STS-48/STM-16 LVDS data stream
into four byte wide STS-12/STM-4 LVTTL data
streams with parity. The B1 parity byte is calculated
over the STS-48/STM-16 frame and over the number
one STS-12/STM-4 frame. The STS-48/STM-16 B1
parity byte is compared to the one received, if an
error exists then B1ERR will be asserted and the
STS-12/STM-4 parity B1 will be inserted with the
same number of bit errors found in the STS-48/STM-
16 B1 parity byte. Also, if no errors exist then the
calculated STS-12/STM-4 B1 will be inserted into the
number one STS-12/STM-4 frame. A frame synchro-
nous descrambler can be optionally disabled by the
DSCRBENB input. The input data stream is moni-
tored for Loss of Signal (LOS) and Out of Frame
(OOF) and alarms are generated for each one.
The frame counter receives the FRAME signal indi-
cating the frame boundaries and counts 38,880
bytes (9 rows x 90 columns x 48 STS-1) to ensure
that the receiver is receiving synchronous FRAME
pulses. The frame counter keeps track of the over-
head bytes so that proper location and insertion of
bytes is accomplished. In diagnostic loopback mode,
a loopback frame (LB_FRAME) signal is generated
internally and the FRAME input is disabled.
Clock Generation
The clock generation circuitry generates the 77.76
MHz POCLK clock required for the byte wide STS-12/
STM-4 interface from the 311 MHz clock (311CLKIN)
required for the byte wide STS-48/STM-16 interface.
B1 Parity Calculation and Compare
The B1 byte is allocated for regeneration section error
monitoring. This byte will be calculated using even
parity. The section bit interleaved parity (BIP-8) error
detection code B1 will be optionally calculated for ev-
ery STS-48/STM-16 frame before descrambling and
for the number one STS-12/STM-4 frame after
descrambling. The B1 value is compared to the ex-
tracted value of the STS-48/STM-16 B1 parity byte
after descrambling in the following frame. B1 errors
will be shown at the B1ERR output when the B1SELB
is active. The calculated STS-12/STM-4 B1 parity
byte will be inserted after descrambling into the num-
ber one STS-12/STM-4 frame if there are no errors
found on the STS-48/STM-16 B1 parity byte. If there
are errors found with the STS-48/STM-16 B1 parity
byte, the number of bit errors (1 to 8) will be passed
onto the STS-12/STM-4 B1 parity byte for insertion
into the number one STS-12/STM-4 frame. The num-
ber one STS-12/STM-4 frame is output on the
POUT[7:0]A data bus. The following functional timing
diagram depicts the B1ERR timing.
Descrambling
The byte wide STS-48/STM-16 data stream is op-
tionally descrambled using the SONET frame syn-
chronous descrambler with a generator polynomial
of 1 + x6 + x7 with a sequence length of 127. The
descrambler algorithm is identical to the scrambler
algorithm. The descrambler will be reset to
“1111111” on the most significant bit of the byte fol-
lowing the last byte of the first row of the STS-12/
STM-4 section overhead. This bit and all subsequent
bits to be descrambled will be added modulo 2 to the
output from the X7 position of the descrambler (A1,
A2, or C1 bytes are not descrambled). The
descrambler will run continuously throughout the
complete STS-48/STM-16 frame. A signal from the
frame counter block controls when the descrambler
is on, off, or reset.
Figure 4. B1 Error (B1ERR) Functional Timing Diagram
POCLK
B1ERR
low for a minimum of 2
clock cycles
7
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
