SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 3. Transmitter Output Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
PCLKA
LVTTL
O
128
127
126
125
Parallel Clock. A 77.76 MHz clock generated by dividing the
internal 311TCLK by four. It is normally used to coordinate byte
wide transfers between the STS-12/STM-4 overhead processors
and the S3045 device.
PCLKB
PCLKC
PCLKD
311DATOUT-
P/N[7:0]
LVDS
O
48–41
39–32
311 Mbit Data. STS-48/STM-16 byte wide data path. A 311
Mbytes/sec word, aligned to the 311 MHz parallel output clock
(311CLKOUT). 311DATOUT [7] is the most significant bit
(corresponding to bit 1 of each word, the first bit transmitted).
311DATOUT[0] is the least significant bit (corresponding to bit 8
of each word, the last bit transmitted).
311CLKOUTP
311CLKOUTN
LVDS
O
O
27
26
311 MHz Clock. 311 CLKOUT is a clock for the transmit STS-
48/STM-16 byte wide data path. A 311 MHz output clock, which
311DATAOUT [7:0] is aligned.
SYNCRSTB
LVTTL
122
Synchronous Reset. Active low. When active, the Network
Interface Processors are reset to synchronize the four STS-
12/STM-4 incoming data streams. Figure 3 shows the S3045
synchronous reset timing diagram.
PARERRA
PARERRB
PARERRC
PARERRD
LVTTL
O
182
145
110
83
Parity Error Output. Active high. Indicates to the controller that a
parity error has been detected on the PIN[7:0] A, B, C, D data bus
on a previous byte of data. When active, a parity error has been
received. When inactive, PIN[7:0] A, B, C, D data has been
received without parity errors. PARERR output can be delayed by
one to five PCLK cycles due to the internal data FIFO. See Figure
10. Note that during a sync reset condition and a hardware reset,
parity errors may erroneously be generated.
READP
READN
LVDS
O
54
53
Read Output. This output is the result of synchronizing the
PULSEP/N input to the 311TCLK input clock through a register.
(Required for operation with the AMCC S3041.)
13
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
