SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 4. Receiver Input Pin Assignment and Descriptions (Continued)
Pin Name
SDVBB
Level
I/O
Pin #
Description
I
190
Signal Detect. Bias pin for the SDLVPECL input. Biased internally
to VDD -1.3V.
FPSEL
LVTTL
I
I
204
207
Frame Pulse Select. When low the FRAME input is used to
generate the FP A, B, C, D pulse when the third A2 byte is output.
When high, the FP A, B, C, D output is internally generated using
the A1A2 frame boundary. The FP A, B, C, D is asserted high when
the third A2 (28h) byte is output. For normal operation set high. This
signal is static and must not be changed in normal operation.
PARFPRXSEL
LVTTL
Parity Frame Pulse Receive Select. When low, parity is calculated
over the data POUT[7:0] A, B, C, D. When high, parity is calculated
over the data POUT[7:0] A, B, C, D and the frame pulse (FP A, B,
C, D) output. This signal is static and must not be changed in normal
operation.
Table 5. Receiver Output Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
POUTA[7:0]
POUTB[7:0]
POUTC[7:0]
POUTD[7:0]
LVTTL
O
168–161 Parallel Data Output. Parallel data bus, a 77.76 Mbyte/sec word,
140–133 aligned to the parallel output clock (POCLK). POUT[7] is the most
106–99 significant bit (corresponding to bit 1 of each word, the first bit
79–72
received). POUT[0] is the least significant bit (corresponding to bit
8 of each word, the last bit received). POUT[7:0], LOS, PAROUT
A, B, C, D, B1ERR, FP A, B, C, D and OOF are updated on the
falling edge of POCLK.
POCLKA
POCLKB
POCLKC
POCLKD
LVTTL
LVTTL
LVTTL
O
O
O
169
141
107
80
Parallel Output Clock. POCLKA, B, C, D are 77.76 MHz byte rate
output clocks that are aligned to POUT[7:0]A, B, C, D byte serial
output data. POUT[7:0] is updated on the falling edge of POCLK.
FPA
FPB
FPC
FPD
157
130
95
Frame Pulse. Indicate frame boundaries in the incoming data
stream. FP pulses high for one POCLK cycle when the third A2 byte
of the framing sequence is valid on the POUTA[7:0] data. FP is
updated on the falling edge of POCLK.
69
OOF
185
Out of Frame. The Out of Frame (OOF) signal is active when the
S3045 has detected an out of frame condition. The OOF is inactive
when the S3045 is in frame. An OOF declaration occurs when four
consecutive errored framing patterns are received. OOF is used to
enable upstream framing pattern detector to search for the framing
pattern. Figure 13 depicts the functional timing of this signal.
15
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
