S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 4. Receiver Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
311DATINN/P
[7:0]
LVDS
I
21–14,
11–4
311 Mbit Data Inputs. Parallel STS-48/STM-16 data bus, a 311
Mbyte/sec word aligned to the parallel input [311CLKIN]. 311DATAIN
[7] is the most significant bit (corresponding to bit 1 of each word, the
first bit received). 311DATAIN [0] is the least significant bit
(corresponding to bit 8 of each word, the last bit received).
311DATAIN [7:0] is latched on the rising edge of 311CLKIN.
311CLKINN
311CLKINP
LVDS
LVDS
I
I
25
24
311 MHz Clock. 311CLKIN is a 311 MHz byte rate input clock that
is aligned to 311DATAIN [7:0] byte serial input data. 311DATIN [7:0]
and FRAME are clocked in on the rising edge of the 311CLKIN.
FRAMEN
FRAMEP
2
1
Frame. Active high. When active, it indicates that the third A2 byte
of the framing sequence is valid on the 311DATIN<7:0> pins.
Therefore it indicates frame boundaries in the incoming data stream
(311DATIN[7:0]).
DSCRBENB
SQUELCHB
LVTTL
LVTTL
I
I
199
201
Descrambler Enable. Active low. When active, the frame
synchronous descrambler is enabled. When inactive the frame
synchronous descrambler is disabled. This signal is static and must
not be changed in normal operation.
Squelch Clock Mode. Active low. Set inactive when a clock recovery
device used provides a continuous clock during signal loss or re-
acquisition. Set active when the clock recovery device used does
not provide a continuous clock during signal loss or signal
acquisition. When active and SDLVPECL/SDLVTTL is inactive
(SDLVPECL and SDLVTTL are in the same logical states) the
transmitter serial clock (311TCLK) will be used to maintain timing
in the receiving section. This signal is static and must not be
changed in normal operation.
SDLVTTL
LVTTL
I
192
Signal Detect. Active High when SDLVPECL is tied to logic 0. Active
Low when SDLVPECL is held at logic 1. A single-ended LVTTL
input to be driven by the external optical receiver module to indicate
a loss of received optical power. When SDLVTTL is inactive, the
data on the 311DATIN[7:0] pins will be internally forced to a
constant zero with the descrambler bypassed. Note: When B1SEL
is active, a B1 byte is inserted into each frame. When SDLVTTL is
active, data on the 311DATIN[7:0] pins will be processed normally.
SDLVPECL
LVPECL
I
191
Signal Detect. Active High when SDLVTTL is held at logic 0. Active
Low when SDLVTTL is held at logic 1. A single-ended LVPECL
input to be driven by the external optical receiver module to indicate
a loss of received optical power. When SDLVPECL is inactive, the
data on the Serial Data in 311DATIN[7:0] pins will be internally
forced to a constant zero with the descrambler bypassed. Note:
When B1SEL is active, a B1 byte is inserted into each frame. When
SDLVPECL is active, data on the 311DATIN[7:0] pins will be
processed normally. When SDLVTTL is to be connected to the
optical receiver module instead of SDLVPECL, then SDLVPECL
should be tied High to implement an active low Signal Detect.
14
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
