S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 2. Transmitter Input Pin Assignment and Descriptions
Pin Name
PICLK
Level
I/O
Pin #
Description
LVTTL
I
129
Parallel Input Clock. PICLK is a 77.76 MHz input clock which
PIN[7:0] is aligned. PICLK is used to transfer the data on the PIN
inputs into a holding register. The rising edge of PICLK samples
PIN A, B, C, D[7:0].
PINA[7:0]
PINB[7:0]
PINC[7:0]
PIND[7:0]
LVTTL
LVTTL
I
I
180–173, Parallel Data Input. A 77.76 Mbytes/sec word, aligned to the
156–149, PICLK parallel input clock. PIN[7] is the most significant bit
121–117, (corresponding to bit 1 of each word, the first bit transmitted).
115–113, PIN[0] is the least significant bit (corresponding to bit 8 of each
94–91,
89–86
word, the last bit transmitted). PIN[7:0] is sampled on the rising
edge of PICLK.
SCRBENB
198
Scramble Enable. Active low. When active, the frame
synchronous scrambler is enabled. When inactive, the scrambler
is disabled. This signal is static and must not be changed in normal
operation.
311TCLKN
311TCLKP
LVDS
I
I
30
31
311 MHz Transmit Clock. Used by the transmitter to generate the
77.76 MHz clocks and retime the STS-48/STM-16 byte wide data.
TIFPA
TIFPB
TIFPC
TIFPD
LVTTL
172
148
112
85
Transmit Input Frame Pulse. Active high. When active, it indicates
the frame position of the transmit data (PIN[7:0]). TIFP goes high
for a single PCLK A, B, C, D (77.76 MHz) period during the first
synchronous payload envelope byte after 12 C1 bytes. TIFP is
clocked in on the rising edge of PICLK.
PARINA
PARINB
PARINC
PARIND
LVTTL
LVTTL
I
I
181
146
111
84
Parity Input. Odd or even parity depending on the input of parity
select (PARSEL) for the 8 bit PIN[7:0] A, B, C, D data bus. PARIN
is clocked in on the rising edge of PICLK.
B2/M1SELB
200
B2/M1 Parity Byte and Parity Count Select. Active low. When
inactive the B2/M1 byte calculations and insertions are disabled.
When active, normal operation occurs (B2 and M1 calculations
and insertions are enabled). This signal is static and must not be
changed in normal operation.
J0/Z0SEL
LVTTL
I
I
205
Section-Trace Insertion Select. Select pin, select section-trace
bytes J0/Z0 options. When low the J0/Z0 bytes are passed
through with no modification. When high, byte 1 of 48 (J0 byte) is
passed though with no modification (transparent) and bytes 2
through 48 (Z0 bytes) are filled with the values of 02hex to 30hex
(48 decimal) respectively. (See Table 1.) This signal is static and
must not be changed in normal operation.
PULSEP
PULSEN
LVDS
52
51
PULSE Input. This input is used to generate the READP/N output
by synchronizing the PULSEP/N input to the 311TCLK input clock
through a register. (Required for operation with the AMCC S3041
OC-48 TX Mux).
PARFPTXSEL
LVTTL
208
Parity Frame Pulse Transmit Select. When low, parity is calculated
over the data bus PIN[7:0] A, B, C, D. When high, parity is
calculated over the PIN[7:0] A, B, C, D data bus and the Transmit
Input Frame Pulse (TIFP A, B, C, D). This signal is static and must
not be changed in normal operation.
12
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
