SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
FP
TTL/
CMOS
O
24
16
Frame pulse, indicates frame boundaries in the
incoming data stream (RSD). If framing pattern
detection is enabled, as controlled by the OOF
input, FP pulses high for one POCLK cycle when a
48-bit sequence matching the framing pattern is
detected on the RSD inputs.
POCLK
TTL/
O
O
O
48
45
52
60
63
56
Parallel output clock, a 77.76 MHz, 19.44 MHz, or
17.408 MHz nominally 50% duty cycle, byte rate
output clock, that is aligned to POUT(7-0) byte serial
output data. POUT(7-0), FP and LCV are updated
on the falling edge of POCLK.
CMOS
BYTCLKIP
LOCKDET
TTL/
CMOS
Reference feedback clock, compared with the
reference clock (REFCLK) to maintain stability of the
clock recovery PLL when it is in loss of signal state.
BYTCLKIP is at the same frequency as REFCLK
and is an asynchronous output.
TTL
Clock recovery indicator. Set high when the internal
clock recovery has locked onto the incoming data
stream. LOCKDET will go low if the incoming
encoded data stream has been low continuously for
4000 to 8000 bit times. LOCKDET will go high if
LOS is low and good data with acceptable run
length and transition density returns on the incoming
data stream. LOCKDET is an asynchronous output.
CAP1
CAP2
–
I
1, 2
79, 80
–
–
The loop filter capacitor is connected to these pins.
The capacitor value should be 0.01µf ±10%
tolerance, X7R dielectric. 50 V is recommended (16
V is acceptable).
AGND
AVEE
GND
–
–
5, 56, 65,
71, 76
32, 37, Analog Ground (0V)
42, 48, 54
–4.5V
4, 57, 63,
67, 73
33, 40, Power Supply (–4.5V)
46, 50, 53
ECLGND
Gnd
–
–
7, 15, 19, 4, 13, 18, ECL Ground (0V)
22, 26, 25, 34,
35, 39, 52, 61, 68
42, 46, 54
VEE
–4.5V
8, 14, 27, 6, 7, 11, Power Supply (–4.5V)
34, 47, 53 24, 30, 62
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
15
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
