SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
REFCLKP
REFCLKN
Diff.
ECL
I
77
75
36
38
Input normally used as the reference for the integral
clock recovery PLL. (See Tables 3 and 4.) When the
test clock enable (TESTEN) input is set high,
REFCLK replaces the bit rate recovered clock. (See
Table 6.)
REFSEL1
REFSEL0
TTL
TTL
I
I
12
11
26
27
Inputs used to select the reference frequency for the
internal clock synthesizer. (See Tables 3 and 4.)
MODE2
MODE1
MODE0
49
10
9
59
28
29
Inputs used to select the operating mode of the
device as 622.08 Mbit/s (STS-12); 155.52 Mbit/s
(STS-3); 155.52 Mbit/s CMI (STS-3 electrical); or
139.764 Mbit/s (E4 CMI). (See Table 2.)
TESTRST
RSTB
TTL
TTL
I
18
17
20
21
Used to reset portions of the clock recovery PLL
during production testing. Held low for normal
operation.
I
Reset input for the device, active low. After reset,
frame boundary detection is disabled.
LLDP
LLDN
Diff.
ECL
O
72
74
41
39
High-speed source-terminated diff. ECL line
loopback data. A regenerated version of either the
incoming data stream (RSD) input in normal mode,
or the diagnostic loopback data (DLD) input in
diagnostic loopback mode (DLEB set high). LLD is
updated on the rising edge of LLCLK.
LLCLKP
LLCLKN
Diff.
ECL
O
O
69
70
44
43
High-speed source-terminated diff. ECL line
loopback clock, phase-aligned with the LLD output
signals. LLCLK can be a buffered version of the
internally recovered bit clock, or the reference clock
(REFCLK) input when clock recovery is bypassed
(TESTEN set high).
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
TTL/
CMOS
37
36
33
32
31
30
29
28
2
3
Parallel data output, a 77.76 Mbyte/s, 19.44
Mbyte/s, or 17.408 Mbyte/s word, aligned to the
POCLK parallel output clock. POUT7 is the most
significant bit (corresponding to bit 1 of each PCM
word, the first bit transmitted). POUT0 is the least
significant bit (corresponding to bit 8 of each PCM
word, the last bit transmitted). POUT(7-0) is updated
on the falling edge of POCLK.
5
8
9
10
12
14
LCV
TTL/
CMOS
O
44
65
Line code violation output signal, set high to indicate
that one or more bits of the byte currently presented
on POUT(7– 0) contains a CMI line code violation.
LCV is only active in STS-3 CMI and E4 CMI
modes. LCV is updated on the falling edge of
POCLK.
Applied Micro Circuits Corporation
14
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
