SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3005 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
DLCV
TTL
TTL
I
I
49
12
59
26
Diagnostic line code violation input. A rising edge
causes a CMI code violation in the serial output
data. DLCV is an asynchronous input which is only
valid when CMI is enabled.
DLEB
Diagnostic loopback enable signal. Enables the DLD
output when low. When DLEB is high, the DLD
output is held in the inactive state to prevent
interference between the transmit and receive
devices. Will not affect the TSD signals.
LLEB
RSTB
TTL
TTL
I
51
9
57
29
Line loopback enable input. When low, the LLD and
LLCLK inputs are connected to the TSD and TSCLK
outputs to implement line loopback. When in normal
mode (LLEB high), the internally generated data and
clock signals are output at TSD and TSCLK.
I
Reset input for the device, active low.
TSDP
TSDN
Diff.
ECL
O
74
72
39
41
High-speed source-terminated serial data stream
signals, normally connected to an optical transmitter
module. Updated on the falling edge of TSCLK.
DLDP
DLDN
Diff.
ECL
O
O
25
24
15
16
High-speed diff. ECL serial data stream signals,
normally connected to a companion S3006 device
for diagnostic loopback purposes. The DLD outputs
are updated on the falling edge of TSCLK. They are
held in the inactive state, except when DLEB is low.
TSCLKP
TSCLKN
Diff.
ECL
69
70
44
43
High-speed source-terminated diff. ECL transmit
serial clock. Phase-aligned with the TSD and DLD
output signals. TSCLK can be a buffered version of
the internal frequency synthesizer clock, of the
REFCLK inputs during clock bypass (TESTEN high),
or of the LLCLK inputs during line loopback (LLEB
low).
PCLK
PAE
TTL/
O
O
16
18
23
20
A reference clock generated by dividing the internal
bit clock by eight. It is normally used to coordinate
byte-wide transfers between upstream logic and the
S3005 device.
CMOS
TTL/
CMOS
Phase alignment event signal, that pulses high
during each PCLK cycle for which there is less than
one bit period between the internal byte clock and
PICLK timing domains. PAE is updated on the
falling edge of the PCLK outputs.
BYTCLKIP
TTL/
CMOS
O
17
21
Reference feedback clock. It is compared with the
reference clock (REFCLK) to maintain stability of the
clock synthesis PLL. BYTCLKIP is at the same
frequency as REFCLK and is an asynchronous
output.
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11
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