SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Table 7. Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Given REFCLK = SERCLK ÷ 8,
12, 16 or 32 per REFSEL<1:0>
settings
Nominal VCO
Center Frequency
622.08
MHz
Given the jitter on REFCLK
(12KHz to 1 MHz band) is less
than:
ECL Data Output Jitter
(S3005 TSDP/N, DLDP/N)
• 56 ps rms (OC–3)
OC–3/STS–3
OC–STS–3 CMI
OC–12/STS-12
64
32
16
ps (rms)
ps (rms)
ps (rms)
• 28 ps rms (OC–STS–3 CMI)
• 14 ps rms (OC–12),
REFCLK = 77.76 MHz
1
Reference Clock
Frequency Tolerance
Clock Synthesis
Required to meet SONET output
frequency specification
S3005 REFCKINP/N
S3006 REFCKINP/N
-20
-100
20
100
ppm
ppm
OC–3/STS–3 &
OC–12/STS–12
Capture Range
±200
ppm
%
With respect to fixed reference
frequency
Minimum transition density of
20%
Lock Range
+8, -12
2
Acquisition Lock Time
OC-3/STS-3
OC-STS-3 CMI
OC-12/STS-12
64
32
16
With device already powered up
and valid REFCLK
µsec
Reference Clock
Input Duty Cycle
30
70
% of period
ns
Reference Clock Rise &
Fall Times
2.0
10% to 90% of amplitude
ECL Output Rise & Fall
Times (S3005 DLDP/N)
20% to 80%, 50Ω to -2V
equivalent load, as per Figure 19
600
450
ps
ps
Source Terminated
Differential ECL
Compatible Outputs
Rise and Fall Times
20% to 80%, 100Ω line to line,
as per Figure 19
1. For REFCLK =19.44, 38.88 or 51.84 MHz, multiply the specified value by three.
2. Specifications based on design values. Not tested.
Applied Micro Circuits Corporation
19
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
