SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
RSDP
RSDN
Diff.
ECL
I
62
64
51
49
High-speed diff. ECL receive serial data stream
signals, normally connected to an optical receiver
module. When internal clock recovery is used, clock
is recovered from transitions on the RSD inputs.
When external clock recovery is used, the RSD
inputs are sampled on the rising edge of the
reference (REFCLK). An internal 100-Ω termination
resistor is connected across RSDP and RSDN.
DLDP
DLDN
Diff.
ECL
I
66
68
47
45
High-speed diff. ECL diagnostic loopback data.
Serial data stream signals, normally connected to a
companion S3005 device for diagnostic loopback
purposes. Clock is recovered from transitions on the
DLD inputs while in diagnostic loopback. An internal
100- termination resistor is connected across
DLDP and DLDN.
DLEB
TTL
TTL
TTL
I
I
I
51
6
57
31
58
Selects diagnostic loopback. When DLEB is high,
the S3006 device uses the primary data (RSD)
input. When low, the S3006 device uses the
diagnostic loopback data (DLD) input.
TESTEN
OOF
Test clock enable signal, set high to provide access
to the PLL during production tests. Can also be
used to enable an external clock source in bypass
mode (see Table 6).
50
Out of frame indicator used to enable framing
pattern detection logic in the S3006. This logic is
enabled by a rising edge on OOF, and remains
enabled until frame boundary is detected or when
OOF is set low, whichever is longer. OOF is an
asynchronous signal with a minimum pulse width of
one POCLK period. (See Figures 17 and 18.)
LOS
ECL
I
16
23
An active-high, single-ended 10K ECL input to be
driven by the external optical receiver module to
indicate a loss of received optical power (Loss of
Signal). When LOS is high, the data on the Serial
Data In (RSDP/N) pins will be internally forced to a
constant zero, LOCKDET will be forced low, and the
PLL will lock to the REFCKINP/N inputs. This signal
must be used to assure correct automatic
reacquisition to serial data following an interruption
and subsequent reconnection of the optical path.
(This ensures that the PLL does not "wander" out of
reacquisition range by tracking the random
phase/frequency content of the optical detector's
noise floor while monitoring "dark" fiber.) When LOS
is low, data on the RSDP/N pins will be processed
normally.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
13
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