SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3005 Pin Assignment and Descriptions
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
TTL
I
37
36
33
32
31
30
29
28
2
3
Parallel data input, a 77.76 Mbyte/s, 19.44 Mbyte/s,
or 17.408 Mbyte/s word, aligned to the PICLK
parallel input clock. PIN7 is the most significant bit
(corresponding to bit 1 of each PCM word, the first
bit transmitted). PIN0 is the least significant bit
(corresponding to bit 8 of each PCM word, the last
bit transmitted). PIN(7-0) is sampled on the rising
edge of PICLK.
5
8
9
10
12
14
PICLK
TTL
I
48
60
Parallel input clock, a 77.76 MHz, 19.44 MHz, or
17.408 MHz nominally 50% duty cycle input clock,
to which PIN(7-0) is aligned. PICLK is used to
transfer the data on the PIN inputs into a holding
register in the parallel-to-serial converter. The rising
edge of PICLK samples PIN(7-0).
TESTEN
SYNC
TTL
TTL
I
I
6
31
58
Test clock enable signal, set high to provide access
to the PLL during production tests. (See Table 6.)
50
Active high synchronization enable input that
enables the timing generator to invert the internal
byte transfer clock if transfers from the PIN(7-0)
input holding register are occurring less than one bit
period before or after clocking new data into the
holding register. The SYNC pin is an asynchronous
input.
REFCLKP
REFCLKN
Diff.
ECL
I
I
I
77
75
36
38
Inputs used as the reference for the internal bit clock
frequency synthesizer, or used as an externally
provided bit clock. (See Tables 3 and 4.)
REFSEL1
REFSEL0
TTL
TTL
10
11
28
27
Inputs used to select the reference frequency for the
internal clock synthesizer. (See Tables 3 and 4.)
MODE2
MODE1
MODE0
43
45
44
66
63
65
Inputs used to select the operating mode of the
device as 622.08 Mbit/s (STS-12); 155.52 Mbit/s
(STS-3); 155.52 Mbit/s CMI (STS-3 electrical); or
139.764 Mbit/s (E4 CMI). (See Table 2.)
LLDP
LLDN
Diff.
ECL
I
I
64
62
49
51
Line loopback data inputs normally provided from a
companion S3006 device. Used to implement a line
loopback, in which the received bit serial data and
clock signals are regenerated and passed through
the S3005 transmitter. An internal 100-Ω resistor
terminates LLDP to LLDN.
LLCLKP
LLCLKN
Diff.
ECL
68
66
45
47
Line loopback clock inputs normally provided from a
companion S3006 device. Used to implement a line
loopback, in which the received bit serial data and
clock signals are regenerated and passed through
the S3005 transmitter. An internal 100-Ω resistor
terminates LLCLKP to LLCLKN.
Applied Micro Circuits Corporation
10
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
