S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 9. S2021 Destination Device Timing
t
period
50_MHZ
(input)
t
t
MPW
MPW
t
t
H25
SU25
1. Control Outputs:
25_MHZ
(input)
PARITY_ERROR
LLRC_ERROR
CONNECT_REQUEST
PACKET_OUTLE
BURST_OUT
t
t
HMS
SUM
MSEL (2:0)
t
t
PWCR
PWCF
WRITE_CLOCK
(output)
t
PDP
2. Control Inputs:
CONNECT_ IN
ACCEPT/REJECT
READY_IN
32 DATA_ + _4 PARITY + SELB
(output)
t
PCO
Control Outputs1
t
PSAV
SOURCE_AVAILABLE, SYNC_ERROR
t
PDV
DATA_VALID
Control Inputs2
t
t
SUIC
HCI
I
t
M PW
READY_IN
(input)
t
RDYPER
t
HRRDY
N RSTRDY
t
SURRDY
S2021 Destination Timing Table
Min
Typ
Max
Notes
nsec
—
5.55
5
nsec
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
nsec
—
—
14
15
—
—
13
13
18
16
—
—
—
—
—
—
—
3
t
t
t
t
t
t
t
t
t
t
t
t
t
PERIOD
3
MPW
4
PWCF
4
5
PWCR
Relative to 50MHz Falling Edge
2
SU25
H25
2.5
—
—
—
—
9
4
PDP
4
PCO
4
PSAV
Relative to WRCLK Falling Edge
4
PDV
SUCI
HCI
0
3
3
RDYPER
SURRDY
40
8
t
t
t
Relative to WRCLK falling edge or RDYIN rising edge
3
8
HRRDY
SUM
HMS
5
t
5
3. Guaranteed but not tested
4. Assumes 5pf load for ECL and 15pf for TTL
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
