S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Data is input to each channel of the S2009 nominally
as 10-bit parallel data. This consists of eight data
bits of user data, KGEN, and DN. An input FIFO and
a clock input, TCLKx, are provided for each channel
of the S2009. The device can operate in two different
modes. In Channel Lock Mode, all four bytes of input
data are clocked into their respective FIFOs using
the TCLKA clock. In Independent Mode, each byte of
data is clocked into its FIFO with the TCLKx pro-
vided with each byte. Table 1 provides a summary of
the input modes for the S2009.
TRANSMITTER DESCRIPTION
The transmitter section of the S2009 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Four channels are
provided with a variety of options regarding input
clocking and loopback. The transmitters can operate
in the range of 1.3 to 1.6 GHz, 20 times the refer-
ence clock frequency.
Data Input
The S2009 has been designed to simplify the paral-
lel interface data transfer and provides the utmost in
flexibility regarding clocking of parallel data. The
S2009 incorporates a unique FIFO structure on both
the parallel inputs and the parallel outputs which en-
ables the user to provide a “clean” reference source
for the PLL and to accept a separate external clock
which is used exclusively to reliably clock data into
the device.
Operation in the TCLK Mode makes it easier for users
to meet the relatively narrow setup and hold time win-
dow required by the parallel 10-bit interface. The
TCLKx signal is used to clock the data into an internal
holding register and the S2009 synchronizes its inter-
nal data flow to insure stable operation. However, re-
gardless of the clock mode, REFCLK is always the
VCO reference clock. This facilitates the provision of a
clean reference clock resulting in minimum jitter on the
serial output. The TCLKx must be frequency locked to
REFCLK, but may have an arbitrary phase relation-
ship. Adjustment of internal timing of the S2009 is per-
formed during reset. Once synchronized, the user must
insure that the timing of the TCLKx signal does not
change by more than ± 3 ns relative to the REFCLK.
Table 1. Input Modes
CH_LOCK
Operation
INDEPENDENT MODE. TCLKx MODE. TCLKx used to clock
data into FIFOs for all channels. (No receiver byte de-skew.)
0
1
CHANNEL LOCK MODE. TCLKA MODE. TCLKA used to
clock data into FIFOs for all channels. (Receiver byte de-skew
active.)
1. Note that internal synchronization of FIFOs is performed upon de-assertion of RESET_N
or when the synchronization pattern is generated (SYNC = 1 DNx = 1).
6
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
