S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Figure 4. Transmitter Block Diagram
RATE
REFCLK
TCLKO
REFCLK
DIN PLL
20x
CH_LOCK
Divide
by 2
TCLKO2
8
SQLA_N
8
DINA[0:7]
10
8B/10B
Encode
TXAP
FIFO
(input)
SYNC
DNA
Shift
Reg
TXAN
TXABP
KGENA
0
1
TCLKA
8
8
8
SQLB_N
8
DINB[0:7]
10
8B/10B
Encode
TXBP
FIFO
(input)
Shift
Reg
TXBN
DNB
TXBBP
KGENB
0
1
TCLKB
SQLC_N
8
10
DINC[0:7]
8B/10B
Encode
TXCP
FIFO
(input)
Shift
Reg
TXCN
DNC
TXCBP
KGENC
0
1
TCLKC
SQLD_N
8
DIND[0:7]
10
8B/10B
Encode
TXDP
FIFO
(input)
Shift
Reg
TXDN
DND
TXDBP
KGEND
0
1
TCLKD
RESET_N
4
February 9, 2001 / Revision C