S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the receive PLL to lock to the
reference clock. This allows the PLL to maintain the
correct frequency in the absence of data.
RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 5.
The ‘lock to reference’ frequency criteria insure that the
S2009 will respond to variations in the serial data input
frequency (compared to the reference frequency). The
New Lock State is dependent upon the current lock
state, as shown in Table 6.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2009 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the decoded data on its parallel outputs.
The run length criteria ensure that the S2009 will re-
spond appropriately and quickly to a loss of signal. The
run length checker flags a condition of consecutive
ones or zeros across 12 parallel words. Thus 119 or
less consecutive ones or zeros does not cause signal
loss, 160 or more causes signal loss, and 120 through
159 may or may not, depending on how the data aligns
across the four clock byte boundaries. When the run
length checker criterion is exceeded, “Loss of Sync”
will report independently on each channel until the
consecutive ones or zeros stream sees a change in
polarity and the receive PLL has locked to the serial
data input.
The S2009 provides the capability to operate with all
four channels locked together (Channel Lock Mode).
Channel lock process and status reporting is de-
scribed below.
Data Input
A differential input receiver is provided for each chan-
nel of the S2009. Each channel has a loopback mode
in which the serial data from the transmitter replaces
external serial data. The loopback function for each
channel is enabled by its respective LPEN input.
If both the off-frequency detect circuitry test and the run
length test are satisfied, the CRU will attempt to lock to
the incoming data. When lock is achieved, “Loss of
Lock” is removed on the ERRx, EOFx, and KFLAGx
status lines. LOLx will report a logic 0 when lock is
achieved (LOLx is an asynchronous, unfiltered signal).
The unfiltered LOLx pins will have a tendency to pulse
High and Low between PLL lock and unlock. When the
PLL is trying to acquire lock, it tends to drift in and out
of lock. This is due to the PLL always trying to lock to
data until it finally achieves lock to the receive data
stream, therefore, during this situation you can have
rapid High and Low changes on the LOLx outputs.
When the receive PLL locks to data, the LOLx signal is
stable. It is possible for the run length test to be satis-
fied due to noise on the inputs, even if no signal is
present. In this case the lock detect status may periodi-
cally assert as the receive PLL frequency approaches
that of the REFCLK.
The high speed serial inputs to the S2009 are internally
biased to VDD-1.3 V. All that is required externally is
AC-coupling and line-to-line differential termination.
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2009. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
Table 6. Lock to Reference Frequency Criteria
Current Lock
State
PLL Frequency
(vs. REFCLK)
New Lock State
< 488 ppm
488 to 732 ppm
> 732 ppm
Locked
Undetermined
Unlocked
In any transfer of PLL control from the serial data to the
reference clock, the RCxP/N outputs remain phase
continuous and glitch free, assuring the integrity of
downstream clocking.
Locked
< 244 ppm
Locked
Unlocked
244 to 366 ppm
> 366 ppm
Undetermined
Unlocked
10
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
