1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
Table 4. Data to 8B/10B Alphabetic Representation
Data Byte
DIN[0:9] or DOUT[0:9]
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
8B/10B Alphanumeric Representation
Table 5. Operating Rates
REFCLK
Serial
TCLKO
TCLKO2
Frequency
Output Rate
Frequency
Frequency
SDR/20
1.3-1.6 GHz
SDR/10
SDR/20
Note: SDR = Serial Data Rate.
Reference Clock Input
Test Functions
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within ±100 ppm of each other to en-
sure that the clock recovery units can lock to the
serial data.
The S2009 can be configured for factory test to aid
in functional testing of the device. When in the test
mode, the internal transmit and receive Voltage Con-
trolled Oscillator (VCO) is bypassed and the refer-
ence clock substituted. This allows full functional
testing of the digital portion of the chip or bypassing
the internal synthesized clock with an external clock
source. (See Other Operating Modes section.)
The frequency of the reference clock is 1/20 the se-
rial data rate. The frequency of the parallel word rate
output, TCLKO, is constant at 1/10 the serial data
rate, while the TCLKO2 output is constant at 1/20
the serial data rate. See Table 5.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET_N signal. The transmit
FIFO is also reset when the special synchronization
pattern (SYNC=1, DN=1) is generated. TCLKO and
TCLKO2 will operate normally regardless of the state
of RESET_N.
Serial Data Outputs
The S2009 provides LVPECL level serial outputs.
The serial ouputs do not require output pulldown re-
sistors. Outputs are designed to perform optimally
when AC-coupled.
When operating in the Channel Lock Mode, the user
must insure that the path length of the four high speed
serial data signals are matched to within 50 bit times
of delay. Failure to meet this requirement may result
in bit errors in the received data or in byte misalign-
ment.
In addition to path length induced timing skew, the
S2009 can tolerate up to ±3 ns of phase drift be-
tween channels after deskewing the outputs.
9
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
