1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
Figure 3. S2009 Input/Output Diagram
TRS
TMS
TCK
TDI
TDO
RESET_N
RATE
REFCLK
TXAP/N
TXBP/N
TCLKO
TCLKO2
SYNC
DINA[0:7]
DNA, KGENA
10
TCLKA
SQLA_N
TXCP/N
TXDP/N
DINB[0:7]
DNB, KGENB
10
TCLKB
SQLB_N
DINC[0:7]
10
DNC, KGENC
TCLKC
SQLC_N
DIND[0:7]
DND, KGEND
10
TCLKD
SQLD_N
LOLA
RXAP/N
ERRA
DOUTA[0:7]
EOFA, KFLAGA
10
RCA P/N
RXBP/N
RXCP/N
RXDP/N
LOLB
ERRB
DOUTB[0:7]
10
EOFB, KFLAGB
RCB P/N
LOLC
ERRC
DOUTC[0:7]
10
EOFC, KFLAGC
RCC P/N
LOLD
ERRD
DOUTD[0:7]
EOFD, KFLAGD
10
RCD P/N
LPENA
LPENB
CH_LOCK
CMODE
LPENC
LPEND
3
February 9, 2001 / Revision C