1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Figure 5. Receiver Block Diagram
CMODE
S2009
RATE
REFCLK
TXABP
EOFA
FIFO
DOUT CRU
Serial-
Parallel
KFLAGA
ERRA
8
8B/10B
Decode
10
(output)
8
Q
Framing
Data
Stretching
Timing
RXAP
RXAN
DOUTA[0:7]
RCAP/N
LOLA
LPENA
TXBBP
EOFB
KFLAGB
ERRB
FIFO
DOUT CRU
Serial-
Parallel
8
8B/10B
Decode
10
(output)
8
RXBP
RXBN
Framing
Data
Stretching
Timing
DOUTB[0:7]
RCBP/N
LOLB
LPENB
TXCBP
EOFC
KFLAGC
ERRC
FIFO
8B/10B
Decode
DOUT CRU
Serial-
Parallel
10
8
(output)
8
Framing
Data
Stretching
Timing
RXCP
RXCN
DOUTC[0:7]
RCCP/N
LOLC
LPENC
TXDBP
EOFD
KFLAGD
ERRD
FIFO
DOUT CRU
Serial-
Parallel
8
10
(output)
8B/10B
Decode
8
Framing
Data
Stretching
Timing
RXDP
RXDN
DOUTD[0:7]
RCDP/N
LOLD
LPEND
CH_LOCK
RESET_N
5
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
