1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Figure 5. Receiver Block Diagram
CMODE
RATE
REFCLK
TXABP
FIFO
(output)
8
S2009
EOFA
KFLAGA
ERRA
8
DOUTA[0:7]
RCAP/N
LOLA
8B/10B
Decode
Framing
Data
Stretching
Timing
10
Q
DOUT CRU
Serial-
Parallel
RXAP
RXAN
LPENA
EOFB
KFLAGB
ERRB
8
DOUTB[0:7]
RCBP/N
LOLB
TXBBP
FIFO
(output)
8
8B/10B
Decode
Framing
Data
Stretching
Timing
10
DOUT CRU
Serial-
Parallel
RXBP
RXBN
LPENB
EOFC
KFLAGC
ERRC
8
DOUTC[0:7]
RCCP/N
LOLC
FIFO
(output)
TXCBP
8
8B/10B
Decode
Framing
Data
Stretching
Timing
10
DOUT CRU
Serial-
Parallel
RXCP
RXCN
LPENC
EOFD
KFLAGD
ERRD
8
DOUTD[0:7]
RCDP/N
LOLD
CH_LOCK
TXDBP
FIFO
(output)
8
8B/10B
Decode
Framing
Data
Stretching
Timing
10
DOUT CRU
Serial-
Parallel
RXDP
RXDN
LPEND
RESET_N
February 9, 2001 / Revision C
5