®
DEVICE
SPECIFICATION
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
GENERAL DESCRIPTION
S2009
S2009
FEATURES
• CMOS Technology
• Broad operating rate range (1.3 - 1.6 Gbps)
- 1.6 Gbps
- 1/2 Rate Operation
• Quad Transmitter with Phase-Lock Loop (PLL)
clock synthesis from low speed reference
• Quad Receiver PLL provides clock and data
recovery
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for
four separate parallel 8-bit channels
• 32-bit parallel TTL interface with internal series
terminated outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O
signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3 V supply, 2.65 W power dissipation
• Compact 23 mm x 23 mm 208 pin
TBGA package
The S2009 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, serial backplanes, and proprietary point to
point links. The chip provides four separate trans-
ceivers which can be operated individually or locked
together for an aggregate data capacity of >5 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel-to-serial and serial-to-parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip quad
receive PLL is used for clock recovery and data re-
timing on the four independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a +3.3 V power supply and dissi-
pates 2.65 watts.
Figure 1 shows the S2009 and S2204 in a Gigabit
Ethernet application. Figure 2 combines the S2009
with a crosspoint switch to demonstrate a serial
backplane application. Figure 3 is the input/output
diagram. Figures 4 and 5 show the transmit and
receive block diagrams, respectively.
APPLICATIONS
•
•
•
•
•
•
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE
SERIAL BP DRIVER
MAC
(ASIC)
QUAD
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204
MAC
(ASIC)
S2009
MAC
(ASIC)
February 9, 2001 / Revision C
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
