1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
Table 16. Power and Ground Signals (Continued)
Pin Name
Qty.
Pin #
Description
PWR
3
B13, B16, Power
C12
GND
1
2
D3
Ground
CAP1
CAP2
D13
C14
Loop Filter pins. The external loop filter capacitor and resistors are connected
to these pins.
NC
2
B9, C7
Not Connected. Used as Test Pins. Do Not Connect.
Table 17. JTAG Test Signals
Pin Name
Level
TTL
TTL
TTL
TTL
TTL
I/O
Pin #
A10
C10
D10
H15
B3
Description
TMS
I
I
I
Test Mode Select. Enables JTAG testing of device.
Test Clock. JTAG test clock.
Test Data In. JTAG data input.
TCK
TDI
Test Data Out. JTAG data output. Can be high impedance under
JTAG controller command.
O
TDO
TRS
TRISTATE
I
Test Reset. Resets JTAG test state machine.
29
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
