S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Table 13. Receiver Output Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin #
Description
DOUTD7
TTL
O
U11
R10
U9
R9
T9
U8
U7
T8
Channel D Receiver Data outputs. Parallel data on this bus is valid
on the rising edge of RCDP in full clock mode and valid on rising
edge of both RCDP and RCDN in half clock mode.
DOUTD6
DOUTD5
DOUTD4
DOUTD3
DOUTD2
DOUTD1
DOUTD0
EOFD
TTL
TTL
O
O
U6
Channel D End of Frame Detected. A High on this output indicates
that a valid K28.5 has been detected and is present on the parallel
data outputs DOUTD[0:7]. (See Table 7.)
KFLAGD
T7
Channel D K-Character Flag. A High in KFLAGD indicates that a
valid control character has been detected. Data present on the
parallel interface DOUTD[0:7] should be used to indicate which
character was received. (See Table 7.)
ERRD
LOLD
TTL
TTL
O
O
T6
Channel D Receive Error. A High on ERRD signifies the
occurrence of either a parity error or an invalid codeword error
during decoding of the received data. (See Table 7.)
C11
Channel D Loss of Lock Detected. LOLD High indicates that the
CRU on channel D has lost bit lock. This signal will deassert when
the CRU has locked to data. When in Channel Lock Mode, this
signal will assert indicating that the channel D CRU is not bit
locked. This will report asynchronously. (See Table 7.)
RCDP
RCDN
TTL
O
T10
U10
Receive Data Clock for Channel D. Parallel receive data,
DOUTD[0:7], EOFD, KFLAGD, and ERRD are valid on the rising
edge of RCDP when in full clock mode and valid on the rising edge
of both RCDP and RCDN in half clock mode.
26
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
