1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
Figure 13. Transmitter Timing (Independent or Channel Lock Mode)
TCLKx, TCLKA
DINx[0:7], DNx,
KGENx,
SYNC
T1
T2
SERIAL DATA OUT
Table 18. S2009 Transmitter Timing (Independent or Channel Lock Mode)
Parameter
Description
Data Setup w.r.t. TCLK
Data Hold w.r.t. TCLK
Min
750
325
Max Units
Conditions
See Note 1.
T1
T2
-
-
ps
ps
Phase drift between TCLKx and
REFCLK
-3
+3
ns
1. All AC measurements are made from the reference voltage levels of the clock (1.4 V) to the valid input or output
data levels (0.8 V or 2.0 V).
Table 19. S2009 TCLKO, TCLKO2, and TCLKx Performance Specifications
Parameter
Description
Min
Typ
Max Units
Conditions
Peak to peak.
TJITTERT
Edge to Edge TCLKO Jitter
130
1.4
156
1.5
ps
ns
ps
ns
See Note 2.
See Figure 19.
TR , TF
TJITTERT2
TR , TF
TCLKO Rise and Fall Times
Edge to Edge TCLKO2 Jitter
TCLKO2 Rise and Fall Times
Peak to peak.
See Note 2.
See Figure 19.
TCLKO2 leads
TTC2 to TC
TCLKO2 to TCLKO Skew
1
2.8
ns
TCLKO, rising edge
to rising edge.
Slew Rate
Duty Cycle
Duty Cycle
Input Slew Rate
2
ns
%
%
See note 1.
See note 1.
See note 1.
TCLKO, TCLKO2 Duty Cycle
TCLKx Input Duty Cycle
40
35
60
65
1. Unless otherwise specified, all AC measurements are made from the reference voltage levels of the clock (1.4 V) to
the valid input or output data levels (0.8 V or 2.0 V).
2. TTL/CMOS AC timing measurements are assumed to have an output load of 10 pF.
33
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
