1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
Table 13. Receiver Output Pin Assignment and Descriptions (Continued)
Pin Name
ERRB
Level
I/O
Pin #
Description
TTL
O
K3
Channel B Receive Error. A High on ERRB signifies the
occurrence of either a parity error or an invalid codeword error
during decoding of the received data. (See Table 7.)
LOLB
TTL
O
D7
Channel B Loss of Lock Detected. LOLB High indicates that the
CRU on channel B has lost bit lock. This signal will deassert when
the CRU has locked to data. When in Channel Lock Mode, this
signal will assert indicating that the channel B CRU is not bit
locked. This will report asynchronously. (See Table 7.)
RCBP
RCBN
TTL
TTL
O
O
U1
T1
Receive Data Clock for Channel B. Parallel receive data,
DOUTB[0:7], EOFB, KFLAGB, and ERRB are valid on the rising
edge of RCBP when in full clock mode and valid on the rising edge
of both RCBP and RCBN in half clock mode.
DOUTC7
DOUTC6
DOUTC5
DOUTC4
DOUTC3
DOUTC2
DOUTC1
DOUTC0
R7
R6
T5
U3
T4
R5
U2
T3
Channel C Receiver Data Outputs. Parallel data on this bus is
valid on the rising edge of RCCP in full clock mode and valid on
the rising edge of both RCCP and RCCN in half clock mode.
EOFC
TTL
TTL
O
O
R2
Channel C End of Frame Detected. A High on this output indicates
that a valid K28.5 has been detected and is present on the parallel
data outputs DOUTC[0:7]. (See Table 7.)
KFLAGC
P3
Channel C K-Character Flag. A High in KFLAGC indicates that a
valid control character has been detected. Data present on the
parallel interface DOUTC[0:7] should be used to indicate which
character was received. (See Table 7.)
ERRC
LOLC
TTL
TTL
O
O
T2
C9
Channel C Receive Error. A High on ERRC signifies the
occurrence of either a parity error or an invalid codeword error
during decoding of the received data. (See Table 7.)
Channel C Loss of Lock Detected. LOLC High indicates that the
CRU on channel C has lost bit lock. This signal will deassert when
the CRU has locked to data. When in Channel Lock Mode, this
signal will assert indicating that the channel C CRU is not bit
locked. This will report asynchronously. (See Table 7.)
RCCP
RCCN
TTL
O
U5
U4
Receive Data Clock for Channel C. Parallel receive data,
DOUTC[0:7], EOFC, KFLAGC, and ERRC are valid on the rising
edge of RCCP when in full clock mode and valid on the rising edge
of both RCCP and RCCN in half clock mode.
25
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
