1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
Table 14. Receiver Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
RXAP
RXAN
Diff.
LVPECL
I
A2
A3
Differential LVPECL compatible inputs for channel A. RXAP is the
positive input, RXAN is the negative. Internally biased to VDD
-1.3 V for AC coupled applications.
RXBP
RXBN
Diff.
LVPECL
I
I
I
A5
B5
Differential LVPECL compatible inputs for channel B. RXBP is the
positive input, RXBN is the negative. Internally biased to VDD
-1.3 V for AC coupled applications.
RXCP
RXCN
Diff.
LVPECL
A8
A9
Differential LVPECL compatible inputs for channel C. RXCP is the
positive input, RXCN is the negative. Internally biased to VDD
-1.3 V for AC coupled applications.
RXDP
RXDN
Diff.
LVPECL
B11
B12
Differential LVPECL compatible inputs for channel D. RXDP is the
positive input, RXDN is the negative. Internally biased to VDD
-1.3 V for AC coupled applications.
Table 15. Receiver Control Signals
Pin Name
Level
I/O
Pin #
Description
LPENA
TTL
I
D14
G14
G15
H14
Loopback Enable. When Low, input source is the high speed serial
input for each channel. When High, the serial output for each
channel is looped back to its input.
LPENB
LPENC
LPEND
CMODE
TTL
I
C2
Clock Mode Control. When Low, the parallel output clocks
(RCxP/N) rate is equal to 1/2 the data rate. When High, the parallel
output clocks (RCxP/N) rate is equal to the data rate. When
CMODE = 0 (data stretching enabled), the last EOF will always
be clocked by RCxP, before non EOF.
Note: All TTL inputs except REFCLK have internal pull-up networks.
27
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
