S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Table 11. Transmitter Output Signals
Pin Name
Level
I/O
Pin #
Description
TXAP
TXAN
Diff.
LVPECL
O
A17
B17
High speed serial outputs for Channel A.
TXBP
TXBN
Diff.
LVPECL
O
O
O
O
O
C17
D17
High speed serial outputs for Channel B.
High speed serial outputs for Channel C.
High speed serial outputs for Channel D.
TXCP
TXCN
Diff.
LVPECL
E17
F16
TXDP
TXDN
Diff.
LVPECL
F17
G17
TCLKO
TTL
TTL
J14
G4
TTL Output Clock at the parallel data rate. This clock is provided
for use by up-stream circuitry.
TCLKO2
TTL Output Clock at the parallel data rate divided by 2. This clock
is provided for use by up-stream circuitry.
22
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
