S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
The following table provides a list of the pins that are JTAG tested. Each port has a Boundary Scan Register
(BSR), unless otherwise noted. The following features are described: the JTAG mode of each register (input,
output2, or internal (refers to an internal package pin)), the direction of the port if it has a boundary scan register
(in or out), and the position of this register on the scan chain.
Table 9. JTAG Pin Assignments
S2009
Pin Name
Core_Scan
Port Name
JTAG
Mode
Routing
Out
S2009
Pin Name
Core_Scan
Port Name
JTAG
Mode
Routing
In Out
In
40
DINB4
tdatain_b (4)
tdatain_b (3)
tdatain_b (2)
tdatain_b (1)
tdatain_b (0)
tclkb
Input
-
-
SYNC
sync
Input
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
-
-
-
-
-
-
DINB3
Input
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
-
CMODE
CH_LOCK
LPEND
LPENC
LPENB
cmode
chan_lock
lpend
Input
DINB2
Input
-
Input
DINB1
Input
-
Input
DINB0
Input
-
lpenc
Input
TCLKB
DNA
Input
-
lpenb
Input
dna
Input
-
LPENA
lpena
Input
KGENA
DINA7
kgena
Input
-
Internal
Internal
Internal
Input
tdatain_a (7)
tdatain_a (6)
tdatain_a (5)
tdatain_a (4)
tdatain_a (3)
tdatain_a (2)
tdatain_a (1)
tdatain_a (0)
tclka
Input
-
DINA6
Input
-
DINA5
Input
-
RESET_N
REFCLK
reset
refclk
10
11
DINA4
Input
-
Input
transmit_clk_buf
_out
DINA3
Input
-
TCLKO
Output2
-
12
DINA2
Input
-
DND
dnd
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DINA1
Input
-
KGEND
DIND7
DIND6
DIND5
DIND4
DIND3
DIND2
DIND1
DIND0
TCLKD
DNC
kgend
DINA0
Input
-
tdatain_d (7)
tdatain_d (6)
tdatain_d (5)
tdatain_d (4)
tdatain_d (3)
tdatain_d (2)
tdatain_d (1)
tdatain_d (0)
tclkd
TCLKA
RCDP
Input
-
rcdp
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output2
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
RCDN
rcdn
-
DOUTD7
DOUTD6
DOUTD5
DOUTD4
DOUTD3
DOUTD2
DOUTD1
DOUTD0
EOFD
rdataout_d (7)
rdataout_d (6)
rdataout_d (5)
rdataout_d (4)
rdataout_d (3)
rdataout_d (2)
rdataout_d (1)
rdataout_d (0)
eofd_d
-
-
-
-
-
-
dnc
-
KGENC
DINC7
DINC6
DINC5
DINC4
DINC3
DINC2
DINC1
DINC0
TCLKC
KGENB
DNB
kgenc
-
tdatain_c (7)
tdatain_c (6)
tdatain_c (5)
tdatain_c (4)
tdatain_c (3)
tdatain_c (2)
tdatain_c (1)
tdatain_c (0)
tclkc
-
KFLAGD
ERRD
kflagd_d
-
errd_d
-
RCCP
rccp
-
RCCN
rccn
-
DOUTC7
DOUTC6
DOUTC5
DOUTC4
DOUTC3
DOUTC2
DOUTC1
DOUTC0
rdataout_c (7)
rdataout_c (6)
rdataout_c (5)
rdataout_c (4)
rdataout_c (3)
rdataout_c (2)
rdataout_c (1)
rdataout_c (0)
-
-
-
-
kgenb
-
dnb
-
DINB7
DINB6
DINB5
tdatain_b (7)
tdatain_b (6)
tdatain_b (5)
-
-
18
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
