S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Table 10. Transmitter Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
DINA7
TTL
I
P12
R12
T13
T12
U13
P11
R11
T11
Transmit Data for Channel A. Parallel data on this bus is clocked
in on the rising edge of TCLKA. (See Table 1.)
DINA6
DINA5
DINA4
DINA3
DINA2
DINA1
DINA0
DNA
TTL
TTL
TTL
I
I
I
U15
U14
U12
DATA_NOT for Channel A. When Low, data present on DINA[0:7]
is 8B/10B encoded and transmitted serially. When High, special
character sequences are generated as indicated in Table 2.
KGENA
TCLKA
K-Character Generation for Channel A. KGENA High causes the
data on DINA[0:7] to be encoded into a K-Character. (See Table
2.)
Transmit Data Clock A. When CH_LOCK is Low, this signal is
used to clock data on DINA[0:7], KGENA, and DNA into the
S2009. When CH_LOCK is High, TCLKA clocks the data into all
four transmit FIFOs.
DINB7
DINB6
DINB5
DINB4
DINB3
DINB2
DINB1
DINB0
TTL
I
R15
P14
T15
R14
U17
U16
P13
T14
Transmit Data for Channel B. Parallel data on this bus is clocked in
on the rising edge of TCLKA or TCLKB. (See Table 1.)
DNB
TTL
TTL
TTL
TTL
I
I
I
I
R16
T16
R13
DATA_NOT for Channel B. When Low, data present on DINB[0:7]
is 8B/10B encoded and transmitted serially. When High, special
character sequences are generated as indicated in Table 2.
KGENB
TCLKB
K-Character Generation for Channel B. KGENB High causes the
data on DINB[0:7] to be encoded into a K-Character. (See Table
2.)
Transmit Data Clock B. When CH_LOCK is Low, this signal is
used to clock data on DINB[0:7], KGENB, and DNB into the
S2009. When CH_LOCK = High, TCLKB must be tied Low.
DINC7
DINC6
DINC5
DINC4
DINC3
DINC2
DINC1
DINC0
M15
N16
M14
R17
P16
N15
T17
N14
Transmit Data for Channel C. Parallel data on this bus is clocked in
on the rising edge of TCLKA or TCLKC. (See Table 1.)
20
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
