Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Table 10. JTAG Pin Assignments (Continued)
Table 10. JTAG Pin Assignments (Continued)
Routing
Out
Routing
Out
S2004 Pin
Name
Core_Scan
Port Name
JTAG
Mode
S2004 Pin
Name
Core_Scan
Port Name
JTAG
Mode
In
In
TDO
jtag_tdo
jtag_tms
jtag_trs
-
-
-
-
-
-
-
-
-
TXCN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TMS
TRS
TXDP
TXDN
RATE
RXAP
RXAN
RXBP
RXBN
RXCP
RXCN
RXDP
RXDN
Pins not JTAG Tested
TXAP
TXAN
TXBP
TXBN
TXCP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 11. Transmitter Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
DINA7
DINA6
DINA5
DINA4
DINA3
DINA2
DINA1
DINA0
TTL
I
P12
R12
T13
T12
U13
P11
R11
T11
Transmit Data for Channel A. Parallel data on this bus is clocked in on the rising edge
of TCLKA or REFCLK. (See Table 1.)
DNA
TTL
I
U15
DATA_NOT. When Low, data present on DINA[0:7] is 8B/10B encoded and transmit-
ted serially. When High, special character/sequences are generated as indicated in
Table 2.
KGENA
TCLKA
TTL
TTL
I
I
U14
U12
K-Character Generation. KGENA High causes the data on DINA[0:7] to be encoded
into a K-Character. (See Table 2.)
Transmit Data Clock A. When TMODE is High, this signal is used to clock Data on
DINA[0:7], KGENA, and DNA into the S2004. When TMODE is Low, TCLKA is
ignored.
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