QT2022/32 - Data Sheet: DS3051
Table 38: Upload Command and Status Register 1.C005h
Registers upload command and Status
Bit
1.C005h
0
1
Register upload Commands (R/W)
bit1 bit0 Command
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
write-> Upload the MDIO registers from external EEPROM.
2
3
Register upload Command Status for the first EEPROM (RO, LH)
bit3 bit2
Command
0
0
1
1
0
1
0
1
idle, no command
command completed
command in progress
previous command failed
4
5
Register upload Command Status for the second EEPROM (RO, LH)
bit3 bit2
Command
0
0
1
1
0
1
0
1
idle, no command
command completed
command in progress
previous command failed
15:6
Reserved (RO)
10.8 I2C Slave Mode for Register Configuration
The MDIO register space can be accessed through the 2-wire serial interface (TWI) bus. This allows the QT2022/
32 to be controlled by an external microprocessor. MDIO register read or write access through the 2-wire interface
is indirect access. The EEPROM_SCL and EEPROM_SDA clock and data pins are used for this feature.
10.8.1 Register Address Mapping
The normal 256 byte I2C address space is divided into lower and upper blocks of 128. The lower block of 128 bytes
is directly available and is used for defining the MDIO device ID and MDIO register starting address. Address loca-
tion 125 (7Dh) stores the MDIO device ID (for the QT2032 devices 1, 2, 3 and 4 are supported; for the QT2022 only
devices 1, 3 and 4 are supported). Address 126 (7Eh) stores the upper byte of the register address to be accessed,
while address 127 (7Fh) stores the lower byte. Address locations 0 - 124 are not used (Reserved - RO).
The upper 128 bytes of the I2C address space are mapped directly to the MDIO registers. The first two bytes in this
range are mapped to the QT2022/32 memory register address defined by the values in I2C address locations 125
- 127 (above); address 128 is mapped to the upper byte of the register and address 129 is mapped to the lower
byte. The following two bytes are mapped directly to the next register in the QT2022/32 register space. Similarly,
each subsequent pair of bytes is mapped to the following QT2022/32 register. In this way, the I2C upper 128 bytes
are mapped to 64 contiguous QT2022/32 memory registers. The memory mapping between the I2C address space
and the MDIO registers is shown in Figure .
For example, if the MDIO address is set to Register 1.C000 (i.e. Device 1, Address C000h), then the I2C address
space 128 - 255 will be mapped to the QT2022/32 register addresses in the range 1.C000h - 1.C063h.
Many of these memory address locations are not defined in the QT2022/32. Reads from these address locations
will return 0; writes to these address locations will be ignored.
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